BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2
8-bit floating-point convert to BFloat16 (vector)
This instruction converts each 8-bit floating-point element from the lower
or upper half of the source vector to BFloat16 while downscaling the value,
and places the results in the 16-bit elements of the destination vector.
BF1CVTL and BF2CVTL convert the elements from the lower half
of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0])
and 2-UInt(FPMR.LSCALE2[5:0]), respectively.
BF1CVTL2 and BF2CVTL2 convert the elements from the upper half
of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0])
and 2-UInt(FPMR.LSCALE2[5:0]), respectively.
The 8-bit floating-point encoding format for BF1CVTL and BF1CVTL2
is selected by FPMR.F8S1. The 8-bit floating-point
encoding format for BF2CVTL and BF2CVTL2 is selected by
FPMR.F8S2.
0
1
0
1
1
1
0
1
x
1
0
0
0
0
1
0
1
1
1
1
0
0
BF1CVTL{2} <Vd>.8H, <Vn>.<Ta>
1
BF2CVTL{2} <Vd>.8H, <Vn>.<Ta>
if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let part : integer = UInt(Q);
let elements : integer = 64 DIV 8;
let issrc2 : boolean = size == '11';
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Ta>
Is an arrangement specifier,
CheckFPMREnabled(); AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(64) = Vpart{}(n, part);
var result : bits(128);
for e = 0 to elements-1 do
result[e*:16] = FP8ConvertBF(operand[e*:8], issrc2, FPCR(), FPMR());
end;
V{128}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1