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<instructionsection id="BFCVT_float" title="BFCVT -- A64" type="instruction">
  <docvars>
    <docvar key="convert-type" value="single-to-bf16"/>
    <docvar key="instr-class" value="float"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="BFCVT"/>
  </docvars>
  <heading>BFCVT</heading>
  <desc>
    <brief>
      <para>Single-precision convert to BFloat16 (scalar)</para>
    </brief>
    <authored>
      <para>This instruction converts the single-precision floating-point value
in the 32-bit SIMD&amp;FP source register to BFloat16 format and writes
the result in the 16-bit SIMD&amp;FP destination register.</para>
      <para><register_link id="AArch64-id_aa64isar1_el1.xml" state="AArch64">ID_AA64ISAR1_EL1</register_link>.BF16 indicates whether this instruction is supported.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Single-precision to BFloat16" oneof="1" id="iclass_single_precision_to_bfloat16" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="convert-type" value="single-to-bf16"/>
        <docvar key="instr-class" value="float"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="BFCVT"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_BF16" name="v8Ap6"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.simd_dp.floatdp1.BFCVT_BS_floatdp1" tworows="1">
        <box hibit="31" name="M" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="30" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="ftype" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="6" name="opcode" usename="1" settings="6" psbits="xxxxxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="14" width="5" settings="5">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="BFCVT_BS_floatdp1" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="convert-type" value="single-to-bf16"/>
          <docvar key="instr-class" value="float"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="BFCVT"/>
        </docvars>
        <asmtemplate><text>BFCVT  </text><a hover="Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field." link="Hd">&lt;Hd&gt;</a><text>, </text><a hover="Is the 32-bit name of the SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field." link="Sn">&lt;Sn&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.simd_dp.floatdp1.BFCVT_BS_floatdp1" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_BF16) then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="BFCVT_BS_floatdp1" symboldefcount="1">
      <symbol link="Hd">&lt;Hd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 16-bit name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="BFCVT_BS_floatdp1" symboldefcount="1">
      <symbol link="Sn">&lt;Sn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the SIMD&amp;FP source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.simd_dp.floatdp1.BFCVT_BS_floatdp1" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">AArch64_CheckFPEnabled();

let operand : bits(32) = V{}(n);
let merge : boolean = IsMerging(FPCR());
var result : bits(128) = if merge then V{128}(d) else Zeros{128};

result[0+:16] = FPConvertBF(operand, FPCR());
V{128}(d) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
