CASB, CASAB, CASALB, CASLB Compare and swap byte in memory This instruction reads an 8-bit byte from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write. If the destination register is not one of WZR or XZR, CASAB and CASALB load from memory with acquire semantics. CASLB and CASALB store to memory with release semantics. CASB has neither acquire nor release semantics. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, is restored to the values held in the register before the instruction was executed. For a CASB or CASAB instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASB, CASAB, CASALB, or CASLB access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASB, CASAB, CASALB, or CASLB access to succeed when it does occur. A code sequence starting with a CASB or CASAB instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASB, CASAB, CASALB, or CASLB to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: The sequence does not contain any direct system register writes, address translation instructions, cache or TLB maintenance operations, exception producing instructions, exception returns, or ISB barriers. The execution of the sequence includes 32 or fewer instructions. The value provided in <Ws> or <Xs> of the first CASB or CASAB is a value likely to result in the comparison failing. A failing comparison result may lead to better performance due to the hardware not performing a write to memory. For a CASB or CASAB instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, the value in memory is not modified, because the CASB or CASAB either fails its compare or writes the same value back to memory. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 CASB <Ws>, <Wt>, [<Xn|SP>{, #0}] 1 0 CASAB <Ws>, <Wt>, [<Xn|SP>{, #0}] 1 1 CASALB <Ws>, <Wt>, [<Xn|SP>{, #0}] 0 1 CASLB <Ws>, <Wt>, [<Xn|SP>{, #0}] if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF); end; let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let acquire : boolean = L == '1' && t != 31; let release : boolean = o0 == '1'; let tagchecked : boolean = n != 31; <Ws> Is the 32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field. <Wt> Is the 32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. var address : bits(64); var comparevalue : bits(8); var newvalue : bits(8); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_CAS, acquire, release, tagchecked, privileged, t, s); comparevalue = X{8}(s); newvalue = X{8}(t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let data : bits(8) = MemAtomic{}(address, comparevalue, newvalue, accdesc); X{32}(s) = ZeroExtend{32}(data); 2026-03-12 12:23:09 2025-09_rel_asl1