CASP, CASPA, CASPAL, CASPL Compare and swap pair of words or doublewords in memory This instruction reads a pair of 32-bit words or 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the comparison is not equal, the architecture permits writing the value read from the location to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes. CASPA and CASPAL load from memory with acquire semantics. CASPL and CASPAL store to memory with release semantics. CASP has neither acquire nor release semantics. The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails. If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is <Ws> and <W(s+1)>, or <Xs> and <X(s+1)>, are restored to the values held in the registers before the instruction was executed. For a CASP or CASPA instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, this signals to the memory system that an additional subsequent CASP, CASPA, CASPAL, or CASPL access to the specified location is likely to occur in the near future. The memory system can respond by taking actions that are expected to enable the subsequent CASP, CASPA, CASPAL, or CASPL access to succeed when it does occur. A code sequence starting with a CASP or CASPA instruction for which <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, and ending with a subsequent CASP, CASPA, CASPAL, or CASPL to the same location, exhibits the following properties for best performance when the location may be accessed concurrently, on one or more other PEs: The sequence does not contain any direct system register writes, address translation instructions, cache or TLB maintenance operations, exception producing instructions, exception returns, or ISB barriers. The execution of the sequence includes 32 or fewer instructions. The value provided in <Ws> or <Xs> of the first CASP or CASPA is a value likely to result in the comparison failing. A failing comparison result may lead to better performance due to the hardware not performing a write to memory. For a CASP or CASPA instruction, when <Ws> or <Xs> specifies the same register as <Wt> or <Xt>, the value in memory is not modified, because the CASP or CASPA either fails its compare or writes the same value back to memory. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 CASP <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] 0 1 0 CASPA <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] 0 1 1 CASPAL <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] 0 0 1 CASPL <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}] 1 0 0 CASP <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] 1 1 0 CASPA <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] 1 1 1 CASPAL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] 1 0 1 CASPL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}] if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF); end; if Rs[0] == '1' || Rt[0] == '1' then EndOfDecode(Decode_UNDEF); end; let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let datasize : integer{} = 32 << UInt(sz); let acquire : boolean = L == '1'; let release : boolean = o0 == '1'; let tagchecked : boolean = n != 31; <Ws> Is the 32-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Ws> must be an even-numbered register. <W(s+1)> Is the 32-bit name of the second general-purpose register to be compared and loaded. <Wt> Is the 32-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Wt> must be an even-numbered register. <W(t+1)> Is the 32-bit name of the second general-purpose register to be conditionally stored. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xs> Is the 64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register. <X(s+1)> Is the 64-bit name of the second general-purpose register to be compared and loaded. <Xt> Is the 64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register. <X(t+1)> Is the 64-bit name of the second general-purpose register to be conditionally stored. var address : bits(64); var comparevalue : bits(2*datasize); var newvalue : bits(2*datasize); var data : bits(2*datasize); let s1 : bits(datasize) = X{}(s); let s2 : bits(datasize) = X{}(s+1); let t1 : bits(datasize) = X{}(t); let t2 : bits(datasize) = X{}(t+1); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_CAS, acquire, release, tagchecked, privileged, t, t+1, s, s+1); comparevalue = if BigEndian(accdesc.acctype) then s1::s2 else s2::s1; newvalue = if BigEndian(accdesc.acctype) then t1::t2 else t2::t1; if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; data = MemAtomic{2*datasize}(address, comparevalue, newvalue, accdesc); if BigEndian(accdesc.acctype) then X{datasize}(s) = data[2*datasize-1:datasize]; X{datasize}(s+1) = data[datasize-1:0]; else X{datasize}(s) = data[datasize-1:0]; X{datasize}(s+1) = data[2*datasize-1:datasize]; end; 2026-03-12 12:23:09 2025-09_rel_asl1