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<instructionsection id="CBHLO_regs" title="CBHLO -- A64" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="CBHLO"/>
    <docvar key="datatype" value="16"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="CBHHI"/>
    <docvar key="sve-compare-type" value="hi"/>
  </docvars>
  <heading>CBHLO</heading>
  <desc>
    <brief>
      <para>Compare unsigned lower than halfwords and branch</para>
    </brief>
    <authored>
      <para>This instruction compares the unsigned halfword values in two registers, and conditionally
branches to a label at a PC-relative offset if the second value is lower than the first.
This instruction provides a hint that this is not a subroutine call or return.
This instruction does not affect the condition flags.</para>
    </authored>
  </desc>
  <aliasto refiform="cbhcc_regs.xml" iformid="CBHcc_regs">CBH&lt;cc&gt;</aliasto>
  <classes>
    <iclass name="Branch" oneof="1" id="iclass_branch" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="datatype" value="16"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="CBHHI"/>
        <docvar key="sve-compare-type" value="hi"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_CMPBR" name="v9Ap6"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.control.compbranch_regs2.CBHHI_16_regs.CBHLO" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="cc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="14" name="H" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="13" width="9" name="imm9" usename="1">
          <c colspan="9"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="CBHLO_CBHHI_16_regs" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="sve-compare-type" value="hi"/>
          <docvar key="datatype" value="16"/>
          <docvar key="mnemonic" value="CBHHI"/>
          <docvar key="alias_mnemonic" value="CBHLO"/>
        </docvars>
        <asmtemplate><text>CBHLO  </text><a hover="Is the 32-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="WmOrWZR__2">&lt;Wm&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose register to be tested, encoded in the &quot;Rt&quot; field." link="WtOrWZR">&lt;Wt&gt;</a><text>, </text><a hover="Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as &quot;imm9&quot; times 4." link="imm9_offset">&lt;label&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="cbhcc_regs.xml#CBHHI_16_regs">CBHHI</a><text>  </text><a hover="Is the 32-bit name of the general-purpose register to be tested, encoded in the &quot;Rt&quot; field." href="cbhcc_regs.xml#WtOrWZR">&lt;Wt&gt;</a><text>, </text><a hover="Is the 32-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." href="cbhcc_regs.xml#WmOrWZR__2">&lt;Wm&gt;</a><text>, </text><a hover="Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as &quot;imm9&quot; times 4." href="cbhcc_regs.xml#imm9_offset">&lt;label&gt;</a></asmtemplate>
          <aliascond>Never</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CBHLO_CBHHI_16_regs" symboldefcount="1">
      <symbol link="WmOrWZR__2">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CBHLO_CBHHI_16_regs" symboldefcount="1">
      <symbol link="WtOrWZR">&lt;Wt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CBHLO_CBHHI_16_regs" symboldefcount="1">
      <symbol link="imm9_offset">&lt;label&gt;</symbol>
      <account encodedin="imm9">
        <intro>
          <para>Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range -1024 to 1020, is encoded as "imm9" times 4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
