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<instructionsection id="CINC_CSINC" title="CINC -- A64" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="CINC"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="CSINC"/>
  </docvars>
  <heading>CINC</heading>
  <desc>
    <brief>
      <para>Conditional increment</para>
    </brief>
    <authored>
      <para>This instruction returns, in the destination register,
the value of the source register incremented by 1 if the
condition is TRUE, and otherwise returns the value of the
source register.</para>
    </authored>
  </desc>
  <operationalnotes/>
  <aliasto refiform="csinc.xml" iformid="CSINC">CSINC</aliasto>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="CSINC"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A64.dpreg.condsel.CSINC_32_condsel.CINC" tworows="1">
        <box hibit="31" width="1" name="sf" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="30" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="29" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1" settings="5" constraint="!= 11111">
          <c colspan="5">!= 11111</c>
        </box>
        <box hibit="15" width="4" name="cond" usename="1" settings="3" psbits="xxxx" constraint="!= 111x">
          <c colspan="4">!= 111x</c>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="o2" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1" settings="5" constraint="!= 11111">
          <c colspan="5">!= 11111</c>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="CINC_CSINC_32_condsel" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CSINC"/>
          <docvar key="alias_mnemonic" value="CINC"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <asmtemplate><text>CINC  </text><a hover="Is the 32-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="WdOrWZR">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose source register, encoded in the &quot;Rn&quot; and &quot;Rm&quot; fields." link="RmRn_option__3">&lt;Wn&gt;</a><text>, </text><a hover="Is one of the standard conditions, excluding AL and NV, encoded with its least significant bit inverted, and " link="cond_option__2">&lt;invcond&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="csinc.xml#CSINC_32_condsel">CSINC</a><text>  </text><a hover="Is the 32-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." href="csinc.xml#WdOrWZR">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." href="csinc.xml#WnOrWZR__3">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." href="csinc.xml#WmOrWZR__2">&lt;Wm&gt;</a><text>, </text><a hover="Is one of the standard conditions, encoded in the standard way, and " href="csinc.xml#cond_option">&lt;cond&gt;</a></asmtemplate>
          <aliascond>Rn == Rm</aliascond>
        </equivalent_to>
      </encoding>
      <encoding name="CINC_CSINC_64_condsel" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
        <docvars>
          <docvar key="datatype" value="64"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CSINC"/>
          <docvar key="alias_mnemonic" value="CINC"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <asmtemplate><text>CINC  </text><a hover="Is the 64-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="XdOrXZR__6">&lt;Xd&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose source register, encoded in the &quot;Rn&quot; and &quot;Rm&quot; fields." link="RmRn_option__4">&lt;Xn&gt;</a><text>, </text><a hover="Is one of the standard conditions, excluding AL and NV, encoded with its least significant bit inverted, and " link="cond_option__2">&lt;invcond&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="csinc.xml#CSINC_64_condsel">CSINC</a><text>  </text><a hover="Is the 64-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." href="csinc.xml#XdOrXZR__6">&lt;Xd&gt;</a><text>, </text><a hover="Is the 64-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." href="csinc.xml#XnOrXZR__12">&lt;Xn&gt;</a><text>, </text><a hover="Is the 64-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." href="csinc.xml#XmOrXZR__4">&lt;Xm&gt;</a><text>, </text><a hover="Is one of the standard conditions, encoded in the standard way, and " href="csinc.xml#cond_option">&lt;cond&gt;</a></asmtemplate>
          <aliascond>Rn == Rm</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CINC_CSINC_32_condsel" symboldefcount="1">
      <symbol link="WdOrWZR">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CINC_CSINC_32_condsel" symboldefcount="1">
      <symbol link="RmRn_option__3">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CINC_CSINC_32_condsel, CINC_CSINC_64_condsel" symboldefcount="1">
      <symbol link="cond_option__2">&lt;invcond&gt;</symbol>
      <definition encodedin="cond">
        <intro>Is one of the standard conditions, excluding AL and NV, encoded with its least significant bit inverted, and </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">cond</entry>
                <entry class="symbol">&lt;invcond&gt;</entry>
                <entry class="symbol">Description</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">NE</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> EQ.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">EQ</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> NE.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">CC</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> CS.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">CS</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> CC.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">PL</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> MI.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">MI</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> PL.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">VC</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> VS.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">VS</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> VC.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">LS</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> HI.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">HI</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> LS.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">1010</entry>
                <entry class="symbol">LT</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> GE.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">1011</entry>
                <entry class="symbol">GE</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> LT.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">LE</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> GT.</para>
                </entry>
              </row>
              <row>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">GT</entry>
                <entry class="description">
                  <para>Maps to <syntax>&lt;cond&gt;</syntax> LE.</para>
                </entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CINC_CSINC_64_condsel" symboldefcount="1">
      <symbol link="XdOrXZR__6">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CINC_CSINC_64_condsel" symboldefcount="1">
      <symbol link="RmRn_option__4">&lt;Xn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" and "Rm" fields.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
