CMHS (register)
Compare unsigned higher or same (vector)
This instruction compares each vector element in the
first source SIMD&FP register with the corresponding
vector element in the second source SIMD&FP register
and if the first unsigned integer value is greater than or equal to
the second unsigned integer value
sets every bit of the corresponding vector element
in the destination SIMD&FP register to one,
otherwise sets every bit of the corresponding vector element
in the destination SIMD&FP register to zero.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
CMHS D<d>, D<n>, D<m>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size != '11' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = esize;
let elements : integer = 1;
0
1
0
1
1
1
0
1
0
0
1
1
1
1
CMHS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size::Q == '110' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
<m>
Is the number of the second SIMD&FP source register, encoded in the "Rm" field.
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
size
Q
<T>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
0
RESERVED
11
1
2D
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand1 : bits(datasize) = V{}(n);
let operand2 : bits(datasize) = V{}(m);
var result : bits(datasize);
var element1 : integer;
var element2 : integer;
for e = 0 to elements-1 do
element1 = UInt(operand1[e*:esize]);
element2 = UInt(operand2[e*:esize]);
result[e*:esize] = if element1 >= element2 then Ones{esize} else Zeros{esize};
end;
V{datasize}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1