<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2025 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="COSP_SYS" title="COSP -- A64" type="alias">
  <docvars>
    <docvar key="alias_mnemonic" value="COSP"/>
    <docvar key="instr-class" value="system"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="SYS"/>
  </docvars>
  <heading>COSP</heading>
  <desc>
    <brief>
      <para>Clear other speculative prediction restriction by context</para>
    </brief>
    <authored>
      <para>This instruction prevents predictions,
other than Cache prefetch, Control flow, and Data Value predictions,
that predict execution addresses based on information gathered from
earlier execution within a particular execution context.
Predictions, other than Cache prefetch, Control flow, and
Data Value predictions, determined by the actions of code in the target
execution context or contexts appearing in program order before
the instruction cannot exploitatively control any speculative access
occurring after the instruction is complete and synchronized.</para>
    </authored>
  </desc>
  <aliasto refiform="sys.xml" iformid="SYS">SYS</aliasto>
  <classes>
    <iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="system"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="SYS"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_SPECRES2" name="v8Ap9"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.control.systeminstrs.SYS_CR_systeminstrs.COSP" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="4" settings="4">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="20" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="18" width="3" name="op1" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" name="CRn" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="CRm" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="7" width="3" name="op2" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="COSP_SYS_CR_systeminstrs" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="system"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SYS"/>
          <docvar key="alias_mnemonic" value="COSP"/>
        </docvars>
        <asmtemplate><text>COSP  RCTX, </text><a hover="Is the 64-bit name of the general-purpose source register, encoded in the &quot;Rt&quot; field." link="XtOrXZR__3">&lt;Xt&gt;</a></asmtemplate>
        <equivalent_to>
          <asmtemplate><a href="sys.xml#SYS_CR_systeminstrs">SYS</a><text>  #3, C7, C3, #6, </text><a hover="Is the 64-bit name of the first general-purpose register to be conditionally stored, encoded in the &quot;Rt&quot; field. &lt;Xt&gt; must be an even-numbered register." href="sys.xml#Xt">&lt;Xt&gt;</a></asmtemplate>
          <aliascond>Unconditionally</aliascond>
        </equivalent_to>
      </encoding>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="COSP_SYS_CR_systeminstrs" symboldefcount="1">
      <symbol link="XtOrXZR__3">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
