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<instructionsection id="CSNEG" title="CSNEG -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="CSNEG"/>
  </docvars>
  <heading>CSNEG</heading>
  <desc>
    <brief>
      <para>Conditional select negation</para>
    </brief>
    <authored>
      <para>This instruction returns, in the destination register,
the value of the first source register if the condition is TRUE,
and otherwise returns the negated value of the second source register.</para>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="CNEG_CSNEG" aliasfile="cneg_csneg.xml" hover="Conditional negate" punct=".">
      <text>CNEG</text>
      <aliaspref>!(cond IN {'111x'}) &amp;&amp; Rn == Rm</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink/>
      <text> below for details of when the alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="CSNEG"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A64.dpreg.condsel.CSNEG_32_condsel" tworows="1">
        <box hibit="31" width="1" name="sf" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="30" name="op" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="29" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="4" name="cond" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="o2" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="CSNEG_32_condsel" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CSNEG"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <asmtemplate><text>CSNEG  </text><a hover="Is the 32-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="WdOrWZR">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__3">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="WmOrWZR__2">&lt;Wm&gt;</a><text>, </text><a hover="Is one of the standard conditions, encoded in the standard way, and " link="cond_option">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CSNEG_64_condsel" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
        <docvars>
          <docvar key="datatype" value="64"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CSNEG"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <asmtemplate><text>CSNEG  </text><a hover="Is the 64-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="XdOrXZR__6">&lt;Xd&gt;</a><text>, </text><a hover="Is the 64-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="XnOrXZR__12">&lt;Xn&gt;</a><text>, </text><a hover="Is the 64-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="XmOrXZR__4">&lt;Xm&gt;</a><text>, </text><a hover="Is one of the standard conditions, encoded in the standard way, and " link="cond_option">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.dpreg.condsel.CSNEG_32_condsel" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let datasize : integer{} = 32 &lt;&lt; UInt(sf);
let condition : bits(4) = cond;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CSNEG_32_condsel" symboldefcount="1">
      <symbol link="WdOrWZR">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSNEG_32_condsel" symboldefcount="1">
      <symbol link="WnOrWZR__3">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSNEG_32_condsel" symboldefcount="1">
      <symbol link="WmOrWZR__2">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSNEG_32_condsel, CSNEG_64_condsel" symboldefcount="1">
      <symbol link="cond_option">&lt;cond&gt;</symbol>
      <definition encodedin="cond">
        <intro>Is one of the standard conditions, encoded in the standard way, and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">cond</entry>
                <entry class="symbol">&lt;cond&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">EQ</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">NE</entry>
              </row>
              <row>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">CS</entry>
              </row>
              <row>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">CC</entry>
              </row>
              <row>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">MI</entry>
              </row>
              <row>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">PL</entry>
              </row>
              <row>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">VS</entry>
              </row>
              <row>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">VC</entry>
              </row>
              <row>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">HI</entry>
              </row>
              <row>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">LS</entry>
              </row>
              <row>
                <entry class="bitfield">1010</entry>
                <entry class="symbol">GE</entry>
              </row>
              <row>
                <entry class="bitfield">1011</entry>
                <entry class="symbol">LT</entry>
              </row>
              <row>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">GT</entry>
              </row>
              <row>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">LE</entry>
              </row>
              <row>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">AL</entry>
              </row>
              <row>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">NV</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CSNEG_64_condsel" symboldefcount="1">
      <symbol link="XdOrXZR__6">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSNEG_64_condsel" symboldefcount="1">
      <symbol link="XnOrXZR__12">&lt;Xn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSNEG_64_condsel" symboldefcount="1">
      <symbol link="XmOrXZR__4">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="A64.dpreg.condsel.CSNEG_32_condsel" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">var result : bits(datasize);
if ConditionHolds(condition) then
    result = X{datasize}(n);
else
    result = NOT(X{datasize}(m)) + 1;
end;

X{datasize}(d) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
