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<instructionsection id="DCPS2" title="DCPS2 -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="system"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="DCPS2"/>
  </docvars>
  <heading>DCPS2</heading>
  <desc>
    <brief>
      <para>Debug change PE state to EL2</para>
    </brief>
    <authored>
      <para>This instruction, when executed in Debug state:</para>
      <list type="unordered">
        <listitem>
          <content>If executed at EL0 or EL1, changes the current Exception level and SP to EL2 using <register_link id="AArch64-sp_el2.xml" state="AArch64">SP_EL2</register_link>.</content>
        </listitem>
        <listitem>
          <content>Otherwise, if executed at ELx, selects <xref linkend="ARMARM_SP_ELx">SP_ELx</xref>.</content>
        </listitem>
      </list>
      <para>The target Exception level of a DCPS2 instruction is:</para>
      <list type="unordered">
        <listitem>
          <content>EL2 if the instruction is executed at an Exception level that is not EL3.</content>
        </listitem>
        <listitem>
          <content>EL3 if the instruction is executed at EL3.</content>
        </listitem>
      </list>
      <para>When the target Exception level of a DCPS2 instruction is ELx, on executing this instruction:</para>
      <list type="unordered">
        <listitem>
          <content>
            <xref linkend="ARMARM_ELR_ELx">ELR_ELx</xref> becomes <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
        <listitem>
          <content>
            <xref linkend="ARMARM_SPSR_ELx">SPSR_ELx</xref> becomes <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
        <listitem>
          <content>
            <xref linkend="ARMARM_ESR_ELx">ESR_ELx</xref> becomes <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
        <listitem>
          <content>
            <register_link id="AArch64-dlr_el0.xml" state="AArch64">DLR_EL0</register_link> and <register_link id="AArch64-dspsr_el0.xml" state="AArch64">DSPSR_EL0</register_link> become <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
        </listitem>
        <listitem>
          <content>The endianness is set according to <xref linkend="ARMARM_SCTLR_ELx">SCTLR_ELx</xref>.EE.</content>
        </listitem>
      </list>
      <para>This instruction is always <arm-defined-word>UNDEFINED</arm-defined-word> in Non-debug state.</para>
      <para>This instruction is <arm-defined-word>UNDEFINED</arm-defined-word> at the following Exception levels:</para>
      <list type="unordered">
        <listitem>
          <content>All Exception levels if EL2 is not implemented.</content>
        </listitem>
        <listitem>
          <content>At EL0 and EL1 if EL2 is disabled in the current Security state.</content>
        </listitem>
      </list>
      <para>For more information on the operation of the DCPS&lt;n&gt; instructions, see <xref linkend="ARMARM_dcps">DCPS</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="system"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="DCPS2"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A64.control.exception.DCPS2_DC_exception" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="20" width="16" name="imm16" usename="1">
          <c colspan="16"/>
        </box>
        <box hibit="4" width="3" name="op2" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="1" width="2" name="LL" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="DCPS2_DC_exception" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="system"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="DCPS2"/>
        </docvars>
        <asmtemplate><text>DCPS2  {#</text><a hover="Is an optional 16-bit unsigned immediate, in the range 0 to 65535, defaulting to 0 and encoded in the &quot;imm16&quot; field." link="imm__2">&lt;imm&gt;</a><text>}</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.control.exception.DCPS2_DC_exception" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">// Empty.</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="DCPS2_DC_exception" symboldefcount="1">
      <symbol link="imm__2">&lt;imm&gt;</symbol>
      <account encodedin="imm16">
        <intro>
          <para>Is an optional 16-bit unsigned immediate, in the range 0 to 65535, defaulting to 0 and encoded in the "imm16" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.control.exception.DCPS2_DC_exception" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if !Halted() then Undefined(); end;
DCPSInstruction(EL2);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
