<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2025 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="DSB" title="DSB -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="system"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="DSB"/>
  </docvars>
  <heading>DSB</heading>
  <desc>
    <brief>
      <para>Data synchronization barrier</para>
    </brief>
    <authored>
      <para>This instruction is a memory barrier that ensures the completion
of memory accesses, see <xref linkend="ARMARM_BEICEFJH">Data Synchronization Barrier</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="2">
    <alias_list_intro>This instruction is used by the aliases </alias_list_intro>
    <aliasref aliaspageid="PSSBB_DSB" aliasfile="pssbb_dsb.xml" hover="Physical speculative store bypass barrier" punct=" and ">
      <text>PSSBB</text>
      <aliaspref>CRm == '0100'</aliaspref>
    </aliasref>
    <aliasref aliaspageid="SSBB_DSB" aliasfile="ssbb_dsb.xml" hover="Speculative store bypass barrier" punct=".">
      <text>SSBB</text>
      <aliaspref>CRm == '0000'</aliaspref>
    </aliasref>
    <alias_list_outro>
      <text>  See </text>
      <aliastablelink/>
      <text> below for details of when each alias is preferred.</text>
    </alias_list_outro>
  </alias_list>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_memory_barrier">Memory barrier</a>
      <txt> and </txt>
      <a href="#iclass_memory_nxs_barrier">Memory nXS barrier</a>
    </classesintro>
    <iclass name="Memory barrier" oneof="2" id="iclass_memory_barrier" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="dsb-variants" value="dsb-memory"/>
        <docvar key="instr-class" value="system"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="DSB"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A64.control.barriers.DSB_BO_barriers" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="14" settings="14">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="4" name="CRm" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="7" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="6" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="DSB_BO_barriers" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="system"/>
          <docvar key="isa" value="A64"/>
          <docvar key="dsb-variants" value="dsb-memory"/>
          <docvar key="mnemonic" value="DSB"/>
        </docvars>
        <asmtemplate><text>DSB  (</text><a hover="For the &quot;Memory barrier&quot; variant: specifies the limitation on the barrier operation. Values are:" link="CRm_option__2">&lt;option&gt;</a><text>|#</text><a hover="Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the &quot;CRm&quot; field." link="option__2">&lt;imm&gt;</a><text>)</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.control.barriers.DSB_BO_barriers" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">var nXS : boolean = FALSE;

var alias : <a link="DSBAlias" file="shared_pseudocode.xml" hover="type DSBAlias">DSBAlias</a>;
case CRm of
    when '0000' =&gt; alias = DSBAlias_SSBB;
    when '0100' =&gt; alias = DSBAlias_PSSBB;
    otherwise =&gt;   alias = DSBAlias_DSB;
end;

var domain : MBReqDomain;
case CRm[3:2] of
    when '00' =&gt; domain = MBReqDomain_OuterShareable;
    when '01' =&gt; domain = MBReqDomain_Nonshareable;
    when '10' =&gt; domain = MBReqDomain_InnerShareable;
    when '11' =&gt; domain = MBReqDomain_FullSystem;
end;

var types : <a link="MBReqTypes" file="shared_pseudocode.xml" hover="type MBReqTypes">MBReqTypes</a>;
case CRm[1:0] of
    when '00' =&gt; types = MBReqTypes_All; domain = MBReqDomain_FullSystem;
    when '01' =&gt; types = MBReqTypes_Reads;
    when '10' =&gt; types = MBReqTypes_Writes;
    when '11' =&gt; types = MBReqTypes_All;
end;</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="Memory nXS barrier" oneof="2" id="iclass_memory_nxs_barrier" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="dsb-variants" value="dsb-nxs"/>
        <docvar key="instr-class" value="system"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="DSB"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_XS" name="v8Ap7"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.control.barriers.DSB_BOn_barriers" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="14" settings="14">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="2" name="imm2" usename="1">
          <c colspan="2"/>
        </box>
        <box hibit="9" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="7" width="3" name="op2" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
      </regdiagram>
      <encoding name="DSB_BOn_barriers" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="dsb-variants" value="dsb-nxs"/>
          <docvar key="instr-class" value="system"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="DSB"/>
        </docvars>
        <asmtemplate><text>DSB  </text><a hover="For the &quot;Memory nXS barrier&quot; variant: specifies the limitation on the barrier operation. Values are:" link="imm2_option">&lt;option&gt;</a><text>nXS</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.control.barriers.DSB_BOn_barriers" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_XS) then EndOfDecode(Decode_UNDEF); end;
let types : <a link="MBReqTypes" file="shared_pseudocode.xml" hover="type MBReqTypes">MBReqTypes</a> = MBReqTypes_All;
var nXS : boolean = TRUE;
let alias : <a link="DSBAlias" file="shared_pseudocode.xml" hover="type DSBAlias">DSBAlias</a> = DSBAlias_DSB;
var domain : MBReqDomain;

case imm2 of
    when '00' =&gt; domain = MBReqDomain_OuterShareable;
    when '01' =&gt; domain = MBReqDomain_Nonshareable;
    when '10' =&gt; domain = MBReqDomain_InnerShareable;
    when '11' =&gt; domain = MBReqDomain_FullSystem;
end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="DSB_BO_barriers" symboldefcount="1">
      <symbol link="CRm_option__2">&lt;option&gt;</symbol>
      <definition encodedin="CRm">
        <intro>
          <para>For the "Memory barrier" variant: specifies the limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param>
              <content>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. This option is referred to as the full system barrier. Encoded as CRm = <binarynumber>0b1111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ST</param>
              <content>Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b1110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>LD</param>
              <content>Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = <binarynumber>0b1101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISH</param>
              <content>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b1011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHST</param>
              <content>Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b1010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISHLD</param>
              <content>Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = <binarynumber>0b1001</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSH</param>
              <content>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b0111</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHST</param>
              <content>Non-shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b0110</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSHLD</param>
              <content>Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = <binarynumber>0b0101</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSH</param>
              <content>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b0011</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHST</param>
              <content>Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = <binarynumber>0b0010</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSHLD</param>
              <content>Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = <binarynumber>0b0001</binarynumber>.</content>
            </listitem>
          </list>
          <para>All other encodings of "CRm" that are not listed, other than the values <binarynumber>0b0000</binarynumber> and <binarynumber>0b0100</binarynumber>, are reserved and can be encoded using the <syntax>#&lt;imm&gt;</syntax> syntax. All unsupported and reserved options must execute as a full system barrier operation, but software must not rely on this behavior. For more information on whether an access is before or after a barrier instruction, see <xref linkend="BEIIECBH">Data Memory Barrier (DMB)</xref> or see <xref linkend="BEICEFJH">Data Synchronization Barrier (DSB)</xref>.</para>
          <note>
            <para>The value <binarynumber>0b0000</binarynumber> is used to encode <instruction>SSBB</instruction> and the value <binarynumber>0b0100</binarynumber> is used to encode <instruction>PSSBB</instruction>.</para>
          </note>
        </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">CRm</entry>
                <entry class="symbol">&lt;option&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">OSHLD</entry>
              </row>
              <row>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">OSHST</entry>
              </row>
              <row>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">OSH</entry>
              </row>
              <row>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">NSHLD</entry>
              </row>
              <row>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">NSHST</entry>
              </row>
              <row>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">NSH</entry>
              </row>
              <row>
                <entry class="bitfield">1x00</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">ISHLD</entry>
              </row>
              <row>
                <entry class="bitfield">1010</entry>
                <entry class="symbol">ISHST</entry>
              </row>
              <row>
                <entry class="bitfield">1011</entry>
                <entry class="symbol">ISH</entry>
              </row>
              <row>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">LD</entry>
              </row>
              <row>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">ST</entry>
              </row>
              <row>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">SY</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="DSB_BOn_barriers" symboldefcount="2">
      <symbol link="imm2_option">&lt;option&gt;</symbol>
      <definition encodedin="imm2">
        <intro>
          <para>For the "Memory nXS barrier" variant: specifies the limitation on the barrier operation. Values are:</para>
          <list type="param">
            <listitem>
              <param>SY</param>
              <content>Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. This option is referred to as the full system barrier. Encoded as imm2 = <binarynumber>0b11</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>ISH</param>
              <content>Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as imm2 = <binarynumber>0b10</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>NSH</param>
              <content>Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as imm2 = <binarynumber>0b01</binarynumber>.</content>
            </listitem>
            <listitem>
              <param>OSH</param>
              <content>Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as imm2 = <binarynumber>0b00</binarynumber>.</content>
            </listitem>
          </list>
        </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">imm2</entry>
                <entry class="symbol">&lt;option&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">OSH</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">NSH</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">ISH</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">SY</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="DSB_BO_barriers" symboldefcount="1">
      <symbol link="option__2">&lt;imm&gt;</symbol>
      <account encodedin="CRm">
        <intro>
          <para>Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="A64.control.barriers.DSB_BO_barriers" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">case alias of
    when DSBAlias_SSBB =&gt;
        SpeculativeStoreBypassBarrierToVA();
    when DSBAlias_PSSBB =&gt;
        SpeculativeStoreBypassBarrierToPA();
    when DSBAlias_DSB =&gt;
        if !nXS &amp;&amp; IsFeatureImplemented(FEAT_XS) then
            nXS = PSTATE.EL IN {EL0, EL1} &amp;&amp; IsHCRXEL2Enabled() &amp;&amp; HCRX_EL2().FnXS == '1';
        end;
        DataSynchronizationBarrier(domain, types, nXS);
    otherwise =&gt;
        unreachable;
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
