Reserved
0 0000 0 0 0 0 0
Reserved
00 000000000
UNALLOCATED
00 != 000000000
UNALLOCATED
!= 00
SME encodings
1 0000 1 0 0 0 0
SME2 Quarter Tile Outer Product - 16-bit and 32-bit
00 x00xxxxx0x00000 0xx0xx 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SME2 FP32 non-widening quarter tile outer product
0 0 0 x0
UNALLOCATED
0 0 0 x1 0
SME2 FP8 to FP32 quarter tile outer product
0 1 0 00
SME2 FP8 to FP16 quarter tile outer product
0 1 0 01 0
UNALLOCATED
0 1 0 10 1
UNALLOCATED
0 1 0 1x 0
SME2 BF16 to FP32 quarter tile outer product
1 0 0 x0
SME2 FP16 non-widening quarter tile outer product
1 0 0 x1 0
SME2 FP16 to FP32 quarter tile outer product
1 1 0 x0
SME2 BF16 non-widening quarter tile outer product
1 1 0 x1 0
SME2 Int16 to Int32 quarter tile outer product
0 1 x1
UNALLOCATED
1 1 x1
UNALLOCATED
0 x1 1
SME2 Int8 to Int32 quarter tile outer product
1 x0
UNALLOCATED
00 x00xxxxx0x00000 1xx0xx
UNALLOCATED
00 x00xxxxx0x00001 xxx0xx
UNALLOCATED
00 x00xxxxx0x0001x xxx0xx
UNALLOCATED
00 x00xxxxx0x001xx xxx0xx
UNALLOCATED
00 x00xxxxx0x01xxx xxx0xx
UNALLOCATED
00 x00xxxxx1x0xxxx xxx0xx
SME2 Sparse Outer Product
00 x01xxxxxxx0xxxx xxx0xx 1 0 0 0 0 0 0 0 1 0 0
SME2 FP32 non-widening sparse outer product
0 0 0 0 0
UNALLOCATED
0 0 0 0 1 0
SME2 FP8 to FP32 sparse outer product
0 1 0 0 0
SME2 FP8 to FP16 sparse outer product
0 1 0 0 1 0
SME2 BF16 to FP32 sparse outer product
1 0 0 0 0
SME2 FP16 non-widening sparse outer product
1 0 0 0 1 0
SME2 FP16 to FP32 sparse outer product
1 1 0 0 0
SME2 BF16 non-widening sparse outer product
1 1 0 0 1 0
SME2 Int16 to Int32 sparse outer product
0 1 0 1
UNALLOCATED
1 1 0 1
UNALLOCATED
0 0 1 1
SME Int8 to Int32 sparse outer product
1 0 0
UNALLOCATED
1
UNALLOCATED
00 x0xxxxxxxx0xxxx xxx1xx
UNALLOCATED
00 x0xxxxxxxx1xxxx
SME FP Outer Product - 32 bit
00 x10xxxxxxxxxxxx xx00xx 1 0 0 0 0 0 0 1 0 0 0
SME FP32 outer product
0 0
SME2 FP8 to FP32 widening outer product
0 1 0
UNALLOCATED
0 1 1
SME BF16 widening outer product
1 0
SME FP16 widening outer product
1 1
SME2 Outer Product - Misc
00 x10xxxxxxxxxxxx xx10xx 1 0 0 0 0 0 0 1 0 1 0
SME2 32-bit binary outer product
0 0
SME2 FP8 to FP16 widening outer product
0 1 0 0
UNALLOCATED
0 1 1 0
UNALLOCATED
0 1 1
SME2 FP16 non-widening outer product
1 0 0
SME2 BF16 non-widening outer product
1 1 0
UNALLOCATED
1 1
SME2 Multi-vector - Memory (Contiguous)
01 00xxxxxxxxxxxxx 1 0 1 0 0 0 0 0 0
SME2 multi-vec contiguous load (scalar plus scalar, two registers)
00x 0
SME2 multi-vec contiguous load (scalar plus scalar, four registers)
00x 1 0
SME2 multi-vec contiguous store (scalar plus scalar, two registers)
01x 0
SME2 multi-vec contiguous store (scalar plus scalar, four registers)
01x 1 0
UNALLOCATED
0x1 1 1
SME2 multi-vec contiguous load (scalar plus immediate, two registers)
100 0
SME2 multi-vec contiguous load (scalar plus immediate, four registers)
100 1 0
SME2 multi-vec contiguous store (scalar plus immediate, two registers)
110 0
SME2 multi-vec contiguous store (scalar plus immediate, four registers)
110 1 0
UNALLOCATED
1x1
UNALLOCATED
xx0 1 1
SME2 Multi-vector - Memory (Strided)
01 10xxxxxxxxxxxxx 1 0 1 0 0 0 0 1 0
SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)
00x 0
SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)
00x 1 0
SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)
01x 0
SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)
01x 1 0
UNALLOCATED
0x1 1 1
SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)
100 0
SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)
100 1 0
SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)
110 0
SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)
110 1 0
UNALLOCATED
1x1
UNALLOCATED
xx0 1 1
SME Integer Outer Product - 32 bit
01 x10xxxxxxxxxxxx xxx0xx 1 0 1 0 0 0 0 1 0 0
SME2 Int16 two-way outer product
0 1
UNALLOCATED
1 1
SME Int8 outer product
0
UNALLOCATED
0x x10xxxxxxxxxxxx xxx1xx
SME2 Quarter Tile Outer Product - 64-bit
0x x11xxxxx0000000 0x1xxx 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
SME2 FP64 non-widening quarter tile outer product
0 0 0
UNALLOCATED
0 0 1
UNALLOCATED
0 1
SME2 Int16 to Int64 quarter tile outer product
1
UNALLOCATED
0x x11xxxxx0000000 1x1xxx
UNALLOCATED
0x x11xxxxx0000001 xx1xxx
UNALLOCATED
0x x11xxxxx000001x xx1xxx
UNALLOCATED
0x x11xxxxx00001xx xx1xxx
UNALLOCATED
0x x11xxxxx0001xxx xx1xxx
UNALLOCATED
0x x11xxxxx001xxxx xx1xxx
UNALLOCATED
0x x11xxxxx01xxxxx xx1xxx
UNALLOCATED
0x x11xxxxx1xxxxxx xx1xxx
SME Outer Product - 64 bit
0x x11xxxxxxxxxxxx xx0xxx 1 0 0 0 0 0 1 1 0
SME FP64 outer product
0 0 0
UNALLOCATED
0 0 1
UNALLOCATED
0 1
SME Int16 outer product
1
SME zero array
10 0000010xxxxxxxx 1 1 0 0 0 0 0 0 0 0 0 0 1 0
SME zero array
0000000000
UNALLOCATED
!= 0000000000
SME2 Multiple Zero
10 0000011xxxxxxxx 1 1 0 0 0 0 0 0 0 0 0 0 1 1
SME multiple vectors zero array
0000000000
UNALLOCATED
!= 0000000000
SME2 zero lookup table
10 0010010xxxxxxxx
SME2 Move Lookup Table
10 0010011xxxxxxxx 1 1 0 0 0 0 0 0 0 1 0 0 1 1
SME2 move from lookup table
0 00
UNALLOCATED
0 10
SME2 move into lookup table
1 00
SME2 move vector to lookup table
1 10 0
UNALLOCATED
1 10 1
UNALLOCATED
x1
UNALLOCATED
10 00x011xxxxxxxxx
SME2 Expand Lookup Table (Non-contiguous)
10 010011xxxxxxxxx 1 1 0 0 0 0 0 0 1 0 0 1 1
SME2 lookup table two source registers expand to four non-contiguous destination registers
011 00 0 00
UNALLOCATED
011 00 1 00
SME2 lookup table expand four non-contiguous registers
10 00
UNALLOCATED
x0 01
SME2 lookup table expand two non-contiguous registers
x1 0x
UNALLOCATED
1x
UNALLOCATED
!= 011 00 00
UNALLOCATED
10 011011xxxxxxxxx
SME2 Expand Lookup Table (Contiguous)
10 01x001xxxxxxxxx 1 1 0 0 0 0 0 0 1 0 0 1
UNALLOCATED
0 00x00 00
UNALLOCATED
0 01000 00
SME2 lookup table two source registers expand to four contiguous destination registers
0 01100 0 00
UNALLOCATED
0 01100 1 00
UNALLOCATED
0 1xx00 00
SME2 lookup table expand four contiguous registers
0 xxx10 00
UNALLOCATED
0 xxxx0 10
SME2 lookup table expand two contiguous registers
0 xxxx1 x0
UNALLOCATED
0 x1
SME2 lookup table expand one register
1
SME Move into Array
10 0xx000x0xxxxxxx x0xxxx 1 1 0 0 0 0 0 0 0 0 0 0 0
SME2 move vector to array, two registers
00 1 00 010 x0 0
SME2 move vector to array, four registers
00 1 00 011 00 0
UNALLOCATED
00 1 00 011 10 0
UNALLOCATED
00 1 01 01x x0 0
SME move vector to array
0
SME2 move vector to tile, two registers
1 0x 000 x0 0
SME2 move vector to tile, four registers
1 0x 001 00 0
UNALLOCATED
1 0x 001 10 0
UNALLOCATED
1 0x 0xx x0 1
UNALLOCATED
1 0x 0xx x1
UNALLOCATED
1 0x 1xx
UNALLOCATED
1 1x
UNALLOCATED
!= 00 1 0x 01x x0 0
UNALLOCATED
10 0xx000x0xxxxxxx x1xxxx
SME Move from Array
10 0xx000x1xxxxxxx 1 1 0 0 0 0 0 0 0 0 0 1
SME2 move array to vector, two registers
00 1 00 010 00 x0
SME2 zeroing move array to vector, two registers
00 1 00 010 10 x0
SME2 move array to vector, four registers
00 1 00 011 00 00
SME2 zeroing move array to vector, four registers
00 1 00 011 10 00
UNALLOCATED
00 1 00 011 x0 10
UNALLOCATED
00 1 01 01x x0 x0
SME zeroing move array to vector
0 000 1x
SME move array to vector
0 0x
UNALLOCATED
0 != 000 1x
SME2 move tile to vector, two registers
1 0x 000 00 x0
SME2 zeroing move tile to vector, two registers
1 0x 000 10 x0
SME2 move tile to vector, four registers
1 0x 001 00 00
SME2 zeroing move tile to vector, four registers
1 0x 001 10 00
UNALLOCATED
1 0x 001 x0 10
UNALLOCATED
1 0x 0xx x0 x1
UNALLOCATED
1 0x 0xx x1
UNALLOCATED
1 0x 1xx
UNALLOCATED
1 1x
UNALLOCATED
!= 00 1 0x 01x x0 x0
SME Add Vector to Array
10 0xx010xxxxxxxxx xx0xxx 1 1 0 0 0 0 0 0 0 1 0 0
UNALLOCATED
0
SME add vector to array
1 00 0
UNALLOCATED
1 00 1
UNALLOCATED
1 != 00
UNALLOCATED
10 0xx010xxxxxxxxx xx1xxx
UNALLOCATED
10 0xx1xxxxxxxxxxx
SME2 Multi-vector - Multiple and Single Array Vectors (Two registers)
10 10x10xxxx0xxxxx 1 1 0 0 0 0 0 1 0 1 0 0
SME2 multiple and single vector FP8 long long FMA two sources
0 000 000 1
UNALLOCATED
0 000 != 000 1
SME2 single-multi long FMA two sources
0 010
SME2 multiple and single vector long FMA one source
0 011
SME2 single-multi FP dot product two registers
0 100
SME2 single-multi mixed dot product two registers
0 101 x1x
UNALLOCATED
1 000 1
SME2 single-multi long MLA two sources
1 010
SME2 multiple and single vector long MLA one source
1 011
UNALLOCATED
1 100
SME2 single-multi two-way dot product two registers
1 101 x1x
SME2 single-multi long long MLA two sources
000 0
SME2 multiple and single vector long long FMA one source
001
SME2 single-multi four-way dot product two registers
101 x0x
SME2 single-multi ternary FP two registers
110 0xx
SME2 single-multi ternary int two registers
110 1xx
SME2 single-multi ternary FP16 two registers
111 0xx
UNALLOCATED
111 1xx
SME2 Multi-vector - Multiple and Single Array Vectors (Four registers)
10 10x11xxxx0xxxxx 1 1 0 0 0 0 0 1 0 1 1 0
SME2 multiple and single vector FP8 long long FMA four sources
0 000 000 1
UNALLOCATED
0 000 != 000 1
SME2 multiple and single vector FP8 long long FMA one source
0 001 000
UNALLOCATED
0 001 001
SME2 single-multi long FMA four sources
0 010
SME2 multiple and single vector FP8 long FMA one source
0 011 00x
UNALLOCATED
0 0x1 01x
UNALLOCATED
0 0x1 1xx
SME2 single-multi FP dot product four registers
0 100
SME2 single-multi mixed dot product four registers
0 101 x1x
UNALLOCATED
1 000 1
SME2 single-multi long MLA four sources
1 010
UNALLOCATED
1 0x1
UNALLOCATED
1 100
SME2 single-multi two-way dot product four registers
1 101 x1x
SME2 single-multi long long MLA four sources
000 0
SME2 single-multi four-way dot product four registers
101 x0x
SME2 single-multi ternary FP four registers
110 0xx
SME2 single-multi ternary int four registers
110 1xx
SME2 single-multi ternary FP16 four registers
111 0xx
UNALLOCATED
111 1xx
SME2 Multi-vector - Multiple Array Vectors (Two registers)
10 11x1xxxx00xxxxx 1 1 0 0 0 0 0 1 1 1 0 0
SME2 multiple vectors FP8 long long FMA two sources
0 000 1 000 0
UNALLOCATED
0 000 1 001 0
UNALLOCATED
0 000 1 10x 0
UNALLOCATED
0 000 1 x0x 1
SME2 multiple vectors long FMA two sources
0 010 0 xx0
SME2 multiple vectors FP8 long FMA two sources
0 010 1 000
UNALLOCATED
0 010 1 100
UNALLOCATED
0 010 1 x01
UNALLOCATED
0 0x1 1
SME2 multiple vectors FP dot product two registers
0 100 x0x
SME2 multiple vectors mixed-sign dot product two registers
0 101 0 01x
UNALLOCATED
0 101 0 11x
UNALLOCATED
0 110 1 x0x
UNALLOCATED
0 1x1 1
UNALLOCATED
0 xx0 1 x1x
SME2 multiple vectors long MLA two sources
1 010 0 xx0
UNALLOCATED
1 100 0 x0x
SME2 multiple vectors two-way dot product two registers
1 101 0 x1x
UNALLOCATED
1 1
SME2 multiple vectors binary FP two registers
00 00 111 0 0xx
SME2 multiple vectors binary int two registers
00 00 111 0 1xx
SME2 multiple vectors binary FP16 two registers
00 10 111 0 0xx
UNALLOCATED
00 10 111 0 1xx
UNALLOCATED
00 x1 111 0
SME2 multiple vectors long long MLA two sources
000 0 0
UNALLOCATED
000 0 1
UNALLOCATED
010 0 xx1
UNALLOCATED
0x1 0
SME2 multiple vectors ternary FP16 two registers
100 0 x1x
SME2 multiple vectors four-way dot product two registers
101 0 x0x
SME2 multiple vectors ternary FP two registers
110 0 0xx
SME2 multiple vectors ternary int two registers
110 0 1xx
UNALLOCATED
!= 00 111 0
SME2 Multi-vector - Multiple Array Vectors (Four registers)
10 11x1xxxx10xxxxx 1 1 0 0 0 0 0 1 1 1 1 0
SME2 multiple vectors FP8 long long FMA four sources
0 x0 000 01 000 0
UNALLOCATED
0 x0 000 01 001 0
UNALLOCATED
0 x0 000 01 10x 0
UNALLOCATED
0 x0 000 01 x0x 1
SME2 multiple vectors long FMA four sources
0 x0 010 00 xx0
SME2 multiple vectors FP8 long FMA four sources
0 x0 010 01 000
UNALLOCATED
0 x0 010 01 100
UNALLOCATED
0 x0 010 01 x01
UNALLOCATED
0 x0 0x1 01
SME2 multiple vectors FP dot product four registers
0 x0 100 0x x0x
SME2 multiple vectors mixed dot product four registers
0 x0 101 00 01x
UNALLOCATED
0 x0 101 00 11x
UNALLOCATED
0 x0 110 01 x0x
UNALLOCATED
0 x0 1x1 01
UNALLOCATED
0 x0 xx0 01 x1x
SME2 multiple vectors long MLA four sources
1 x0 010 00 xx0
UNALLOCATED
1 x0 100 00 x0x
SME2 multiple vectors two-way dot product four registers
1 x0 101 00 x1x
UNALLOCATED
1 x0 01
SME2 multiple vectors binary FP four registers
00 00 111 00 0xx
SME2 multiple vectors binary int four registers
00 00 111 00 1xx
SME2 multiple vectors binary FP16 four registers
00 10 111 00 0xx
UNALLOCATED
00 10 111 00 1xx
SME2 multiple vectors long long MLA four sources
x0 000 00 0
UNALLOCATED
x0 000 00 1
UNALLOCATED
x0 010 00 xx1
UNALLOCATED
x0 0x1 00
SME2 multiple vectors ternary FP16 four registers
x0 100 00 x1x
SME2 multiple vectors four-way dot product four registers
x0 101 00 x0x
SME2 multiple vectors ternary FP four registers
x0 110 00 0xx
SME2 multiple vectors ternary int four registers
x0 110 00 1xx
UNALLOCATED
x0 1x
UNALLOCATED
x1
UNALLOCATED
!= 00 x0 111 00
SME2 Multi-vector - Indexed (One register)
10 1xx00xxxxxxxxxx 1 1 0 0 0 0 0 1 0 0
SME2 multi-vec indexed long long MLA one source 32-bit
00
SME2 multi-vec indexed FP8 long long FMA one source
01 000
UNALLOCATED
01 != 000
SME2 multi-vec indexed long long MLA one source 64-bit
10 0 xx0
UNALLOCATED
10 0 xx1
SME2 multi-vec indexed long FMA one source
10 1
SME2 multi-vec indexed FP8 long FMA one source
11 0 0xx
UNALLOCATED
11 0 1xx
SME2 multi-vec indexed long MLA one source
11 1
SME2 Multi-vector - Indexed (Two registers)
10 1xx01xxxx0xxxxx 1 1 0 0 0 0 0 1 0 1 0
SME2 multi-vec indexed long long MLA two sources 32-bit
00 0x
SME2 multi-vec ternary indexed two registers 16-bit
00 1x
SME2 multi-vec ternary indexed two registers 32-bit
01
SME2 multi-vec indexed long long MLA two sources 64-bit
10 00 0
UNALLOCATED
10 01 0
SME2 multi-vec indexed FP8 long long FMA two sources
10 0x 1 00
UNALLOCATED
10 0x 1 != 00
SME2 multi-vec indexed long FMA two sources
10 1x 0
UNALLOCATED
10 1x 1 0x
SME2 multi-vec indexed FP8 long FMA two sources
10 1x 1 1x
SME2 multi-vec ternary indexed two registers 64-bit
11 00 0
SME2 multi-vec indexed FP8 two-way vertical dot product to single-precision two registers
11 01 0
SME2 multi-vec indexed long MLA two sources
11 1x 0
SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers
11 1 0x
UNALLOCATED
11 1 1x
SME2 Multi-vector - Indexed (Four registers)
10 1xx01xxxx1xxxxx 1 1 0 0 0 0 0 1 0 1 1
SME2 multi-vec indexed long long MLA four sources 32-bit
00 0x 0xx
SME2 multi-vec indexed FP8 long long FMA four sources
00 0x 100 0
UNALLOCATED
00 0x 100 1
SME2 multi-vec ternary indexed four registers 16-bit
00 1x 0xx
SME2 multi-vec indexed FP8 two-way dot product to FP16 four registers
00 1x 100
UNALLOCATED
00 101
UNALLOCATED
00 11x
SME2 multi-vec ternary indexed four registers 32-bit
01 0xx
SME2 multi-vec indexed long long MLA four sources 64-bit
10 00 00x
UNALLOCATED
10 01 00x
UNALLOCATED
10 0x 01x
SME2 multi-vec indexed long FMA four sources
10 1x 00x
SME2 multi-vec indexed FP8 long FMA four sources
10 1x 010
UNALLOCATED
10 1x 011
SME2 multi-vec ternary indexed four registers 64-bit
11 0x 00x
SME2 multi-vec indexed long MLA four sources
11 1x 00x
UNALLOCATED
11 01x
UNALLOCATED
!= 00 1xx
SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)
10 1xx10xxxx10100x 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0
SME2 single-multi int min/max two registers
0 00 00x
UNALLOCATED
0 00 101
SME2 single-multi FP min/max two registers
0 01 00x
SME2 multiple and single vector FSCALE two registers
0 01 100
UNALLOCATED
0 01 101
UNALLOCATED
0 0x x1x
SME2 single-multi shift two registers
0 10
SME2 single-multi add two registers
0 11 000
UNALLOCATED
0 11 != 000
SME2 single-multi signed saturating doubling multiply high two registers
1 00 000
UNALLOCATED
1 00 x10
UNALLOCATED
1 00 xx1
UNALLOCATED
1 != 00
UNALLOCATED
00 100
SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)
10 1xx10xxxx10101x xxxx0x 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0
SME2 single-multi int min/max four registers
0 00 00x
UNALLOCATED
0 00 101
SME2 single-multi FP min/max four registers
0 01 00x
SME2 multiple and single vector FSCALE four registers
0 01 100
UNALLOCATED
0 01 101
UNALLOCATED
0 0x x1x
SME2 single-multi shift four registers
0 10
SME2 single-multi add four registers
0 11 000
UNALLOCATED
0 11 != 000
SME2 single-multi signed saturating doubling multiply high four registers
1 00 000
UNALLOCATED
1 00 x10
UNALLOCATED
1 00 xx1
UNALLOCATED
1 != 00
UNALLOCATED
00 100
UNALLOCATED
10 1xx10xxxx10101x xxxx1x
UNALLOCATED
10 1xx11xxxx1010xx
SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)
10 1xx1xxx00101110 xxxx0x 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0
SME2 multiple vectors int min/max four registers
000
UNALLOCATED
001
SME2 multiple vectors FP min/max four registers
010
SME2 multiple vectors FSCALE four registers
011
SME2 multiple vectors shift four registers
10x
UNALLOCATED
11x
SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers)
10 1xx1xxx00101111 xxxx0x 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0
SME2 multi-vector signed saturating doubling multiply high four registers
00000
UNALLOCATED
!= 00000
UNALLOCATED
10 1xx1xxx0010111x xxxx1x
UNALLOCATED
10 1xx1xxx1010111x
SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)
10 1xx1xxxx0101100 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0
SME2 multiple vectors int min/max two registers
000
UNALLOCATED
001
SME2 multiple vectors FP min/max two registers
010
SME2 multiple vectors FSCALE two registers
011
SME2 multiple vectors shift two registers
10x
UNALLOCATED
11x
SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers)
10 1xx1xxxx0101101 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 1
SME2 multi-vector signed saturating doubling multiply high two registers
00000
UNALLOCATED
!= 00000
UNALLOCATED
10 1xx1xxxx01111xx
UNALLOCATED
10 1xx1xxxx11x11xx
SME2 Multi-vector - SVE Select
10 1xx1xxxxx100xxx 1 1 0 0 0 0 0 1 1 1 0 0
SME2 multi-vec select four registers
01 00 00
UNALLOCATED
01 00 10
UNALLOCATED
01 10 x0
UNALLOCATED
11 x0 x0
SME2 multi-vec select two registers
x0 x0 x0
UNALLOCATED
x0 x1
UNALLOCATED
x1
SME2 Multi-vector - SVE Constructive Binary
10 1xx1xxxxx110xxx 1 1 0 0 0 0 0 1 1 1 1 0
SME2 multi-vec quadwords ZIP two registers
00 101
UNALLOCATED
01 101
UNALLOCATED
10 101
SME2 multi-vec saturating shift right narrow two registers
11 101
SME2 multi-vec FCLAMP two registers
000
SME2 multi-vec CLAMP two registers
001
SME2 multi-vec FCLAMP four registers
010 0
SME2 multi-vec CLAMP four registers
011 0
UNALLOCATED
01x 1
SME2 multi-vec ZIP two registers
100
SME2 multi-vec saturating shift right narrow four registers
11x
SME2 Multi-vector - SVE Constructive Unary
10 1xx1xxxxx111000 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0
SME2 multi-vec FP to int convert two registers
00 000 01 x0
SME2 multi-vec int to FP two registers
00 000 10 x0
SME2 multi-vec FP to int convert four registers
00 100 01 0x 00
SME2 multi-vec int to FP four registers
00 100 10 0x 00
SME2 multi-vec FP8 down convert four registers
00 101 00 0x
SME2 multi-vec quadwords ZIP four registers
00 101 11 00 x0
UNALLOCATED
01 000 01 x0
UNALLOCATED
01 001 11
UNALLOCATED
01 101 00 0x 1x
UNALLOCATED
01 10x 00 0x 0x
SME2 multi-vec FP down convert two registers
0x 000 00
SME2 multi-vec int down convert two registers
0x 000 11
SME2 multi-vec FP8 down convert two registers
0x 001 00 x0
UNALLOCATED
0x 001 00 x1
SME2 multi-vec convert two registers
10 000 00
UNALLOCATED
10 001 00 1x
UNALLOCATED
10 x01 00 0x
UNALLOCATED
11 00x 00
UNALLOCATED
11 101 00 0x 1x
UNALLOCATED
11 10x 00 0x 0x
UNALLOCATED
1x 000 11 x1
UNALLOCATED
1x 000 x1 x0
UNALLOCATED
x0 100 00 0x 0x
UNALLOCATED
000 01 x1
UNALLOCATED
000 10 x1
SME2 multi-vec unpack two registers
001 01
SME2 multi-vec FP8 up convert two registers
001 10
SME2 multi-vec FRINT two registers
01x x0 x0
UNALLOCATED
100 01 0x 01
UNALLOCATED
100 01 1x
UNALLOCATED
100 10 0x 01
SME2 multi-vec int down convert four registers
100 11
UNALLOCATED
100 != 11 0x 1x
SME2 multi-vec unpack four registers
101 01 x0 0x
UNALLOCATED
101 01 x0 1x
UNALLOCATED
101 01 x1
SME2 multi-vec ZIP four registers
101 10 00 x0
UNALLOCATED
101 11 1x
UNALLOCATED
101 1x 00 x1
UNALLOCATED
101 1x 01
UNALLOCATED
10x x0 1x
SME2 multi-vec FRINT four registers
11x 00 00
UNALLOCATED
11x 00 10
UNALLOCATED
11x 10 x0
UNALLOCATED
x1x x0 x1
UNALLOCATED
x1x x1
UNALLOCATED
!= 00 000 10 x0
UNALLOCATED
!= 00 100 01 0x 00
UNALLOCATED
!= 00 100 10 0x 00
UNALLOCATED
!= 00 101 11 00 x0
UNALLOCATED
!= 01 001 11
SME2 Multi-vector - FP Multiply
10 1xx1xxxxx111001 0xxxx0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0
SME2 multi-vec FP multiply (four registers)
01 0 0
UNALLOCATED
01 0 1
UNALLOCATED
01 1
UNALLOCATED
11
SME2 multi-vec FP multiply (two registers)
x0
UNALLOCATED
10 1xx1xxxxx111001 0xxxx1
UNALLOCATED
10 1xx1xxxxx111001 1xxxxx
SME2 Multiple and Single Vector - FP multiply
10 1xx1xxxxx111010 0xxxx0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
SME2 multiple and single vector FP multiply (two registers)
0
SME2 multiple and single vector FP multiply (four registers)
1 0 0
UNALLOCATED
1 0 1
UNALLOCATED
1 1
UNALLOCATED
10 1xx1xxxxx111010 0xxxx1
UNALLOCATED
10 1xx1xxxxx111010 1xxxxx
UNALLOCATED
10 1xx1xxxxx111011
SME Memory
11 1 1 1 0 0 0 0
SME load array vector (elements)
0xx0 0xx
SME store array vector (elements)
0xx1 0xx
SME save and restore array
100x 00000 0 xx000 0xx
SME2 lookup table load/store
100x 1 00000 000
UNALLOCATED
100x 1 00000 001
UNALLOCATED
100x 1 00000 01x
UNALLOCATED
100x 1 01000 0xx
UNALLOCATED
100x 1 1x000 0xx
UNALLOCATED
100x xx001 0xx
UNALLOCATED
100x xx01x 0xx
UNALLOCATED
100x xx1xx 0xx
UNALLOCATED
100x != 00000 0 xx000 0xx
UNALLOCATED
101x 0xx
UNALLOCATED
110x 0xx
SME load array vector (quadwords)
1110 0xx
SME store array vector (quadwords)
1111 0xx
UNALLOCATED
1xx
SVE encodings
0010 0 0 1 0
SVE Integer Binary Arithmetic - Predicated
000 0xx0xxxx 000xxx 0 0 0 0 0 1 0 0 0 0 0 0
SVE integer add/subtract vectors (predicated)
00x
SVE integer min/max/difference (predicated)
01x
SVE integer multiply vectors (predicated)
100
SVE integer divide vectors (predicated)
101
SVE bitwise logical operations (predicated)
11x
SVE Integer Reduction
000 0xx0xxxx 001xxx 0 0 0 0 0 1 0 0 0 0 0 1
SVE integer add reduction (predicated)
000
SVE integer add reduction (quadwords)
001
SVE integer min/max reduction (predicated)
010
SVE integer min/max reduction (quadwords)
011
SVE constructive prefix (predicated)
10x
SVE bitwise logical reduction (predicated)
110
SVE bitwise logical reduction (quadwords)
111
SVE Bitwise Shift - Predicated
000 0xx0xxxx 100xxx 0 0 0 0 0 1 0 0 0 1 0 0
SVE bitwise shift by immediate (predicated)
0x
SVE bitwise shift by vector (predicated)
10
SVE bitwise shift by wide elements (predicated)
11
SVE Integer Unary Arithmetic - Predicated
000 0xx0xxxx 101xxx 0 0 0 0 0 1 0 0 0 1 0 1
SVE integer unary operations (predicated)
x0
SVE bitwise unary operations (predicated)
x1
SVE Integer Multiply-Add - Predicated
000 0xx0xxxx x1xxxx 0 0 0 0 0 1 0 0 0 1
SVE integer multiply-accumulate writing addend (predicated)
0
SVE integer multiply-add writing multiplicand (predicated)
1
SVE Bitwise Logical - Unpredicated
000 0xx1xxxx 001xxx 0 0 0 0 0 1 0 0 1 0 0 1
UNALLOCATED
0xx
SVE bitwise logical operations (unpredicated)
100
sve/int-rotate-imm
101
SVE2 bitwise ternary operations
11x
SVE Index Generation
000 0xx1xxxx 0100xx 0 0 0 0 0 1 0 0 1 0 1 0 0
SVE index generation (immediate start, immediate increment)
00
SVE index generation (register start, immediate increment)
01
SVE index generation (immediate start, register increment)
10
SVE index generation (register start, register increment)
11
SVE Stack Allocation
000 0xx1xxxx 0101xx 0 0 0 0 0 1 0 0 1 0 1 0 1
SVE stack frame adjustment
0 0
Streaming SVE stack frame adjustment
0 1
SVE stack frame size
1 0
Streaming SVE stack frame size
1 1
SVE2 Integer Arithmetic - Unpredicated
000 0xx1xxxx 011xxx 0 0 0 0 0 1 0 0 1 0 1 1
SVE2 integer multiply vectors (unpredicated)
0xx
SVE2 signed saturating doubling multiply high (unpredicated)
10x
UNALLOCATED
11x
SVE Bitwise Shift - Unpredicated
000 0xx1xxxx 100xxx 0 0 0 0 0 1 0 0 1 1 0 0
SVE bitwise shift by wide elements (unpredicated)
0
SVE bitwise shift by immediate (unpredicated)
1
SVE Integer Misc - Unpredicated
000 0xx1xxxx 1011xx 0 0 0 0 0 1 0 0 1 1 0 1 1
SVE floating-point trig select coefficient
0x
SVE floating-point exponential accelerator
10
SVE constructive prefix (unpredicated)
11
SVE Element Count
000 0xx1xxxx 11xxxx 0 0 0 0 0 1 0 0 1 1 1
SVE saturating inc/dec vector by element count
0 00x
SVE element count
0 100
UNALLOCATED
0 101
SVE inc/dec vector by element count
1 000
SVE inc/dec register by element count
1 100
UNALLOCATED
1 x01
UNALLOCATED
01x
SVE saturating inc/dec register by element count
11x
SVE Permute Vector - Extract
000 10x1xxxx 000xxx 0 0 0 0 0 1 0 1 0 1 0 0 0
SVE extract vector (immediate offset, destructive)
0
SVE2 extract vector (immediate offset, constructive)
1
SVE Permute Vector - Segments
000 11x1xxxx 000xxx 0 0 0 0 0 1 0 1 1 1 0 0 0
SVE permute vector segments
0
UNALLOCATED
1
SVE Bitwise Immediate
000 1xx00xxx 0 0 0 0 0 1 0 1 0 0
SVE broadcast bitmask immediate
11 00
UNALLOCATED
!= 00
SVE bitwise logical with immediate (unpredicated)
!= 11 00
SVE Integer Wide Immediate - Predicated
000 1xx01xxx 0 0 0 0 0 1 0 1 0 1
SVE copy integer immediate (predicated)
0xx
UNALLOCATED
10x
SVE copy floating-point immediate (predicated)
110
UNALLOCATED
111
SVE Permute Vector - One Source Quadwords
000 1xx1xxxx 001001 0 0 0 0 0 1 0 1 1 0 0 1 0 0 1
sve/int-perm-dupq_i
00
sve/int-perm-extq
01 0
UNALLOCATED
01 1
UNALLOCATED
1x
SVE Permute Vector - Unpredicated
000 1xx1xxxx 001110 0 0 0 0 0 1 0 1 1 0 0 1 1 1 0
SVE broadcast general register
00 000
SVE insert general register
00 100
UNALLOCATED
00 x01
UNALLOCATED
00 x1x
SVE move predicate from vector
01 xx0 0
UNALLOCATED
01 xx0 1
SVE move predicate into vector
01 xx1 0
UNALLOCATED
01 xx1 1
SVE unpack vector elements
10 0xx
SVE insert SIMD&FP scalar register
10 100
UNALLOCATED
10 101
UNALLOCATED
10 11x
SVE reverse vector elements
11 000
UNALLOCATED
11 != 000
UNALLOCATED
000 1xx1xxxx 001111
SVE Permute Predicate
000 1xx1xxxx 010xxx 0 0 0 0 0 1 0 1 1 0 1 0
SVE unpack predicate elements
00 1000x 0000 0
SVE permute predicate elements
0xxxx xxx0 0
SVE reverse predicate elements
10100 0000 0
UNALLOCATED
10101 0000 0
UNALLOCATED
10x0x 0010 0
UNALLOCATED
10x0x 01x0 0
UNALLOCATED
10x0x 1xx0 0
UNALLOCATED
10x1x xxx0 0
UNALLOCATED
11xxx xxx0 0
UNALLOCATED
xxx0 1
UNALLOCATED
xxx1
UNALLOCATED
!= 00 1000x 0000 0
SVE Permute Vector - Predicated
000 1xx1xxxx 10xxxx 0 0 0 0 0 1 0 1 1 1 0
SVE copy SIMD&FP scalar register to vector (predicated)
0 000 0 0
SVE compress Active elements
0 000 1 0
SVE extract element to general register
0 000 1
UNALLOCATED
0 001 1 1
SVE extract element to SIMD&FP scalar register
0 001 0
SVE reverse within elements
0 01x
SVE copy general register to vector (predicated)
0 100 0 1
SVE conditionally broadcast element to vector
0 100 0
SVE conditionally extract element to SIMD&FP scalar
0 101 0
SVE vector splice (destructive)
0 110 0 0
UNALLOCATED
0 110 0 1
SVE2 vector splice (constructive)
0 110 1 0
SVE reverse doublewords
0 111 0
UNALLOCATED
0 111 1 0
UNALLOCATED
0 1xx 1 1
UNALLOCATED
0 x01 0 1
UNALLOCATED
1 000 0 0
sve/int-perm-expand
1 000 1 0
SVE conditionally extract element to general register
1 000 1
UNALLOCATED
1 != 000
SVE Integer Compare - Vectors
001 0xx0xxxx 0 0 1 0 0 1 0 0 0
SVE integer compare vectors
0
SVE integer compare with wide elements
1
SVE Propagate Break
001 1xx00xxx 11xxxx 0 0 1 0 0 1 0 1 0 0 1 1
SVE propagate break from previous partition
0
UNALLOCATED
1
SVE Partition Break
001 1xx01xxx 01xxxx 0 0 1 0 0 1 0 1 0 1 0 1
SVE propagate break to next partition
0 1000 0 0
UNALLOCATED
0 1000 0 1
UNALLOCATED
1 1000 0
SVE partition break condition
0000 0
UNALLOCATED
x000 1
UNALLOCATED
x001
UNALLOCATED
x01x
UNALLOCATED
x1xx
SVE Predicate Misc
001 1xx01xxx 11xxxx 0 0 1 0 0 1 0 1 0 1 1 1
SVE predicate test
0000 x0 0
UNALLOCATED
0000 x1 0
UNALLOCATED
0001 0
SVE predicate first active
1000 000 00 0
UNALLOCATED
1000 000 10 0
SVE predicate zero
1000 100 10 0000 0
UNALLOCATED
1000 100 10 != 0000 0
SVE predicate read from FFR (predicated)
1000 110 00 0
UNALLOCATED
1001 000 00 0
SVE predicate next active
1001 000 10 0
UNALLOCATED
1001 100 10 0
SVE predicate read from FFR (unpredicated)
1001 110 00 0000 0
UNALLOCATED
1001 110 00 != 0000 0
UNALLOCATED
100x 010 x0 0
UNALLOCATED
100x 0x0 x1 0
SVE predicate initialize
100x 100 0x 0
UNALLOCATED
100x 100 11 0
UNALLOCATED
100x 110 != 00 0
UNALLOCATED
100x xx1 0
UNALLOCATED
x00x 1
UNALLOCATED
x01x
UNALLOCATED
x1xx
SVE Predicate Count
001 1xx100xx 10xxxx 0 0 1 0 0 1 0 1 1 0 0 1 0
SVE predicate count (predicate-as-counter)
000 1
SVE predicate count
0
UNALLOCATED
!= 000 1
SVE Inc/Dec by Predicate Count
001 1xx101xx 1000xx 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0
SVE saturating inc/dec vector by predicate count
0 0
SVE saturating inc/dec register by predicate count
0 1
SVE inc/dec vector by predicate count
1 0
SVE inc/dec register by predicate count
1 1
SVE Write FFR
001 1xx101xx 1001xx 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1
SVE FFR write from predicate
0 00 000 00000
SVE FFR initialise
1 00 000 0000 00000
UNALLOCATED
1 00 000 != 0000 00000
UNALLOCATED
00 000 != 00000
UNALLOCATED
00 != 000
UNALLOCATED
!= 00
UNALLOCATED
001 1xx101xx 101xxx
UNALLOCATED
001 1xx11xxx 10xxxx
SVE Integer Compare - Scalars
001 1xx1xxxx 00xxxx 0 0 1 0 0 1 0 1 1 0 0
SVE integer compare scalar count and limit
0x
SVE conditionally terminate scalars
10 00 0000
UNALLOCATED
10 00 != 0000
SVE pointer conflict compare
11 00
UNALLOCATED
1x != 00
SVE Scalar Integer Compare - Predicate-as-counter
001 1xx1xxxx 01xxxx 1 0 0 1 0 0 1 0 1 1 0 1 1
SVE extract mask predicate from predicate-as-counter
00000 110
sve/int-pn_ptrue
00000 111 000000 0
UNALLOCATED
00000 111 000000 1
UNALLOCATED
00000 111 != 000000
SVE integer compare scalar count and limit (predicate pair)
01x
SVE integer compare scalar count and limit (predicate-as-counter)
x0x
UNALLOCATED
!= 00000 11x
SVE Integer Wide Immediate - Unpredicated
001 1xx1xxxx 11xxxx 0 0 1 0 0 1 0 1 1 1 1
SVE integer add/subtract immediate (unpredicated)
00
SVE integer min/max immediate (unpredicated)
01
SVE integer multiply immediate (unpredicated)
10
SVE broadcast integer immediate (unpredicated)
11 0
SVE broadcast floating-point immediate (unpredicated)
11 1
UNALLOCATED
010 0x10xxxx 11001x
SVE Integer Multiply-Add - Unpredicated
010 0xx0xxxx 0xxxxx 0 1 0 0 0 1 0 0 0 0
SVE integer dot product (unpredicated)
0000x
SVE2 saturating multiply-add interleaved long
0001x
SVE2 complex integer dot product
001xx
SVE2 complex integer multiply-add
01xxx
SVE2 integer multiply-add long
10xxx
SVE2 saturating multiply-add long
110xx
SVE2 saturating multiply-add high
1110x
SVE mixed sign dot product
11110
UNALLOCATED
11111
SVE2 Integer - Predicated
010 0xx0xxxx 10xxxx 0 1 0 0 0 1 0 0 0 1 0
SVE2 integer pairwise add and accumulate long
0010 1
UNALLOCATED
0011 1
UNALLOCATED
011x 1
SVE2 integer unary operations (predicated)
0x0x 1
SVE2 saturating/rounding bitwise shift left (predicated)
0xxx 0
SVE2 integer halving add/subtract (predicated)
10xx 0
SVE2 integer pairwise arithmetic
10xx 1
SVE2 saturating add/subtract
11xx 0
UNALLOCATED
11xx 1
UNALLOCATED
010 0xx0xxxx 1101x1
SVE Multiply - Indexed
010 0xx1xxxx 0 1 0 0 0 1 0 0 1
SVE integer dot product (indexed)
00000x
SVE2 integer multiply-add (indexed)
00001x
SVE2 saturating multiply-add high (indexed)
00010x
SVE mixed sign dot product (indexed)
00011x
SVE2 saturating multiply-add (indexed)
001xxx
SVE2 complex integer dot product (indexed)
0100xx
UNALLOCATED
0101xx
SVE2 complex integer multiply-add (indexed)
0110xx
SVE2 complex saturating multiply-add (indexed)
0111xx
SVE2 integer multiply-add long (indexed)
10xxxx
SVE2 integer multiply long (indexed)
110xxx
SVE2 saturating multiply (indexed)
1110xx
SVE2 saturating multiply high (indexed)
11110x
SVE2 integer multiply (indexed)
111110
UNALLOCATED
111111
SVE2 Widening Integer Arithmetic
010 1xx0xxxx 0xxxxx 0 1 0 0 0 1 0 1 0 0
SVE2 integer add/subtract long
0x
SVE2 integer add/subtract wide
10
SVE2 integer multiply long
11
SVE Misc
010 1xx0xxxx 10xxxx 0 1 0 0 0 1 0 1 0 1 0
SVE2 bitwise shift left long
0 10xx
UNALLOCATED
1 10xx
SVE2 integer add/subtract interleaved long
00xx
SVE2 bitwise exclusive-OR interleaved
010x
SVE integer matrix multiply accumulate
0110
UNALLOCATED
0111
SVE2 bitwise permute
11xx
SVE2 Accumulate
010 1xx0xxxx 11xxxx 0 1 0 0 0 1 0 1 0 1 1
SVE2 complex integer add
0000 011
SVE2 integer absolute difference and accumulate long
00x
SVE2 integer add/subtract long with carry
010
SVE2 bitwise shift right and accumulate
10x
SVE2 bitwise shift and insert
110
SVE2 integer absolute difference and accumulate
111
UNALLOCATED
!= 0000 011
SVE2 Narrowing
010 1xx1xxxx 0xxxxx 0 1 0 0 0 1 0 1 1 0
SVE2 saturating extract narrow
0 00 0 10
SME2 multi-vec extract narrow
0 00 1 10 0 0
UNALLOCATED
0 00 1 10 0 1
UNALLOCATED
0 00 1 10 1
SVE2 bitwise shift right narrow
0 0x
UNALLOCATED
0 != 00 10
SME2 multi-vec shift narrow
1 0x 0 0
UNALLOCATED
1 0x 0 1
UNALLOCATED
1 0x 1
UNALLOCATED
1 10
SVE2 integer add/subtract narrow high part
11
SVE2 Histogram Computation (Segment) and Lookup Table
010 1xx1xxxx 101xxx 0 1 0 0 0 1 0 1 1 1 0 1
UNALLOCATED
0 0x1
SVE2 lookup table with 4-bit indices and 8-bit element size
1 001
UNALLOCATED
1 011
SVE2 histogram generation (segment)
000
SVE2 lookup table with 2-bit indices and 8-bit element size
100
SVE2 lookup table with 4-bit indices and 16-bit element size
1x1
SVE2 lookup table with 2-bit indices and 16-bit element size
x10
SVE2 Crypto Extensions
010 1xx1xxxx 111xxx 0 1 0 0 0 1 0 1 1 1 1 1
SVE2 crypto unary operations
000 00 00x 00000
UNALLOCATED
000 00 00x != 00000
UNALLOCATED
000 01 00x
SVE2 crypto destructive binary operations
000 1x 00x
SVE2 multi-vector AES single round (two registers)
xx0 1x 01x
SVE2 multi-vector AES single round (four registers)
xx1 1x 01x
UNALLOCATED
00 01x
UNALLOCATED
01 01x
SVE2 crypto constructive binary operations
10x
SVE2 Multi-vector polynomial multiply long
110 0
SVE2 Multi-vector polynomial multiply long and accumulate vectors
111 0
UNALLOCATED
11x 1
UNALLOCATED
!= 000 00x
UNALLOCATED
011 01x1xxxx 111000
UNALLOCATED
011 0x01xxxx 0111xx
SVE2 FP8 widening multiply-add
011 0x01xxxx 10xx10 0 1 1 0 0 1 0 0 0 1 1 0 1 0
SVE2 FP8 multiply-add long long
0
SVE2 FP8 multiply-add long
1 0
UNALLOCATED
1 1
UNALLOCATED
011 0x01xxxx 10xx11
UNALLOCATED
011 0x01xxxx 11x1xx
UNALLOCATED
011 0x11xxxx 10xx1x
UNALLOCATED
011 0x11xxxx x1x1xx
UNALLOCATED
011 0xx00001 100xxx
UNALLOCATED
011 0xx0010x 100xxx
UNALLOCATED
011 0xx00x0x 11xxxx
UNALLOCATED
011 0xx00x1x 1xxxxx
UNALLOCATED
011 0xx010xx 11xxxx
SVE2 floating-point unary operations - zeroing predicated
011 0xx011xx 1xxxxx 0 1 1 0 0 1 0 0 0 1 1 1
Floating-point round to integral value (predicated)
00x
Floating-point convert (predicated)
010
Floating-point square root (predicated)
011
Floating-point round and convert from integer (predicated)
10x
Floating-point log and convert to integer
11x
UNALLOCATED
011 0xx1xxxx 001011
UNALLOCATED
011 0xx1xxxx 0011xx
SVE floating-point widening multiply-add - indexed
011 0xx1xxxx 01x0xx 0 1 1 0 0 1 0 0 1 0 1 0
SVE BFloat16 floating-point dot product (indexed)
0 0
UNALLOCATED
0 1
SVE floating-point multiply-add long (indexed)
1
SVE floating-point widening multiply-add
011 0xx1xxxx 10x00x 0 1 1 0 0 1 0 0 1 1 0 0 0
SVE BFloat16 floating-point dot product
0 0
UNALLOCATED
0 1
SVE floating-point multiply-add long
1
UNALLOCATED
011 0xx1xxxx 10x10x
UNALLOCATED
011 0xx1xxxx 11101x
UNALLOCATED
011 1xx001xx 0010xx
SVE floating-point unary operations - unpredicated
011 1xx001xx 0011xx 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1
SVE2 FP8 upconverts
00 00x
SVE2 FP8 downconverts
00 010 0
UNALLOCATED
00 010 1
UNALLOCATED
00 011
UNALLOCATED
10x
SVE floating-point reciprocal estimate (unpredicated)
11x 00
UNALLOCATED
11x != 00
UNALLOCATED
!= 00 0xx
SVE floating-point compare - with zero
011 1xx010xx 001xxx 0 1 1 0 0 1 0 1 0 1 0 0 0 1
SVE floating-point compare with zero
0
UNALLOCATED
1
SVE floating-point accumulating reduction
011 1xx011xx 001xxx 0 1 1 0 0 1 0 1 0 1 1 0 0 1
SVE floating-point serial reduction (predicated)
0
UNALLOCATED
1
SVE floating-point arithmetic - predicated
011 1xx0xxxx 100xxx 0 1 1 0 0 1 0 1 0 1 0 0
SVE floating-point arithmetic (predicated)
0x
SVE floating-point trig multiply-add coefficient
10 000
UNALLOCATED
10 != 000
SVE floating-point arithmetic with immediate (predicated)
11 0000
UNALLOCATED
11 != 0000
SVE floating-point unary operations - merging predicated
011 1xx0xxxx 101xxx 0 1 1 0 0 1 0 1 0 1 0 1
SVE floating-point round to integral value
00x
SVE floating-point convert precision
010
SVE floating-point unary operations
011
SVE integer convert to floating-point
10x
SVE floating-point convert to integer
11x
SVE floating-point multiply-add
011 1xx1xxxx 0 1 1 0 0 1 0 1 1
SVE floating-point multiply-accumulate writing addend
0
SVE floating-point multiply-accumulate writing multiplicand
1
SVE Memory - 32-bit Gather and Unsized Contiguous
100 1 0 0 0 0 1 0
SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
00 x1 0xx 0
UNALLOCATED
00 x1 0xx 1
SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)
01 x1 0xx
SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)
10 x1 0xx
SVE load predicate register
11 0x 000 0
UNALLOCATED
11 0x 000 1
SVE load vector register
11 0x 010
UNALLOCATED
11 0x 0x1
SVE contiguous prefetch (scalar plus immediate)
11 1x 0xx 0
UNALLOCATED
11 1x 0xx 1
SVE2 32-bit gather non-temporal load (vector plus scalar)
00 10x
SVE contiguous prefetch (scalar plus scalar)
00 110 0
SVE 32-bit gather prefetch (vector plus immediate)
00 111 0
UNALLOCATED
00 11x 1
SVE 32-bit gather load (vector plus immediate)
01 1xx
SVE load and broadcast element
1x 1xx
SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
!= 11 x0 0xx
SVE Memory - Contiguous Load
101 1 0 1 0 0 1 0
SVE contiguous non-temporal load (scalar plus immediate)
00 0 111
SVE contiguous load (quadwords, scalar plus immediate)
00 1 001
SVE load multiple structures (quadwords, scalar plus immediate)
00 1 111
SVE contiguous load (quadwords, scalar plus scalar)
00 100
SVE contiguous non-temporal load (scalar plus scalar)
00 110
SVE load multiple structures (quadwords, scalar plus scalar)
01 100
UNALLOCATED
1x 100
SVE load and broadcast quadword (scalar plus immediate)
0 001
SVE contiguous load (scalar plus immediate)
0 101
SVE contiguous non-fault load (scalar plus immediate)
1 101
SVE load and broadcast quadword (scalar plus scalar)
000
SVE contiguous load (scalar plus scalar)
010
SVE contiguous first-fault load (scalar plus scalar)
011
SVE load multiple structures (scalar plus immediate)
!= 00 0 111
UNALLOCATED
!= 00 1 001
UNALLOCATED
!= 00 1 111
SVE load multiple structures (scalar plus scalar)
!= 00 110
SVE Memory - 64-bit Gather
110 1 1 0 0 0 1 0
SVE2 128-bit gather load (vector plus scalar)
00 00 101
UNALLOCATED
00 01 0xx 1
SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
00 11 1xx 0
UNALLOCATED
00 11 1
SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
00 x1 0xx 0
SVE 64-bit gather prefetch (vector plus immediate)
00 111 0
UNALLOCATED
00 111 1
SVE2 64-bit gather non-temporal load (vector plus scalar)
00 1x0
SVE 64-bit gather load (vector plus immediate)
01 1xx
SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
10 1xx
SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)
x0 0xx
UNALLOCATED
!= 00 00 101
SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
!= 00 11 1xx
SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
!= 00 x1 0xx
SVE Memory - Non-temporal and Quadword Scatter Store
111 001xxx 1 1 1 0 0 1 0 0 0 1
SVE2 128-bit scatter store (vector plus scalar)
000 1
SVE2 64-bit scatter non-temporal store (vector plus scalar)
xx0 0
SVE2 32-bit scatter non-temporal store (vector plus scalar)
xx1 0
UNALLOCATED
!= 000 1
SVE Memory - Non-temporal and Multi-register Contiguous Store
111 011xxx 1 1 1 0 0 1 0 0 1 1
SVE contiguous non-temporal store (scalar plus scalar)
00
SVE store multiple structures (scalar plus scalar)
!= 00
SVE Memory - Contiguous Store and Unsized Contiguous
111 0x0xxx 1 1 1 0 0 1 0 0 0
SVE store multiple structures (quadwords, scalar plus immediate)
0xx 00 0
UNALLOCATED
0xx 01 0
SVE store multiple structures (quadwords, scalar plus scalar)
0xx 1x 0
UNALLOCATED
10x 0
SVE store predicate register
110 0 0
UNALLOCATED
110 0 1
SVE store vector register
110 1
UNALLOCATED
111 0
SVE contiguous store (scalar plus scalar)
!= 110 1
SVE Memory - Scatter
111 101xxx 1 1 1 0 0 1 0 1 0 1
SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)
00
SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)
01
SVE 64-bit scatter store (vector plus immediate)
10
SVE 32-bit scatter store (vector plus immediate)
11
SVE Memory - Contiguous Store with Immediate Offset
111 111xxx 1 1 1 0 0 1 0 1 1 1
SVE contiguous non-temporal store (scalar plus immediate)
00 1
SVE contiguous store (scalar plus immediate)
0
SVE store multiple structures (scalar plus immediate)
!= 00 1
SVE Memory - Scatter with Optional Sign Extend
111 1x0xxx 1 1 1 0 0 1 0 1 0
SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)
00
SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)
01
SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
10
SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
11
SVE integer add/subtract vectors (unpredicated)
000 0xx1xxxx 000xxx
SVE address generation
000 0xx1xxxx 1010xx
SVE broadcast indexed element
000 1xx1xxxx 001000
SVE table lookup (three sources)
000 1xx1xxxx 00101x
SVE table lookup
000 1xx1xxxx 001100
sve/int-perm-tbxquads
000 1xx1xxxx 001101
SVE permute vector elements
000 1xx1xxxx 011xxx
SVE select vector elements (predicated)
000 1xx1xxxx 11xxxx
SVE integer compare with unsigned immediate
001 0xx1xxxx
SVE predicate logical operations
001 1xx00xxx 01xxxx
SVE integer compare with signed immediate
001 1xx0xxxx x0xxxx
SVE broadcast predicate element
001 1xx1xxxx 01xxxx 0
SVE two-way dot product
010 0000xxxx 11001x
SVE two-way dot product (indexed)
010 0100xxxx 11001x
SVE integer clamp
010 0xx0xxxx 11000x
SVE2 multiply-add (checked pointer)
010 0xx0xxxx 1101x0
SVE permute vector elements (quadwords)
010 0xx0xxxx 111xxx
SVE2 character match
010 1xx1xxxx 100xxx
SVE2 histogram generation (vector)
010 1xx1xxxx 110xxx
SVE2 FP8 matrix multiply-accumulate
011 00x1xxxx 111000
SVE2 FP8 multiply-add long (indexed)
011 0x01xxxx 0101xx
SVE floating-point complex add (predicated)
011 0xx00000 100xxx
SVE floating-point convert (top, predicated)
011 0xx0000x 101xxx
SVE floating-point convert precision odd elements
011 0xx0010x 101xxx
SVE2 floating-point pairwise operations
011 0xx010xx 100xxx
SVE floating-point recursive reduction (quadwords)
011 0xx010xx 101xxx
SVE floating-point complex multiply-add (predicated)
011 0xx0xxxx 0xxxxx
SVE floating-point multiply-add (indexed)
011 0xx1xxxx 0000xx
SVE floating-point complex multiply-add (indexed)
011 0xx1xxxx 0001xx
SVE FP clamp
011 0xx1xxxx 001001
SVE floating-point multiply (indexed)
011 0xx1xxxx 0010x0
SVE2 FP8 multiply-add long long (indexed)
011 0xx1xxxx 1100xx
SVE floating-point matrix multiply accumulate
011 0xx1xxxx 111001
SVE floating-point recursive reduction
011 1xx000xx 001xxx
SVE floating-point arithmetic (unpredicated)
011 1xx0xxxx 000xxx
SVE floating-point compare vectors
011 1xx0xxxx x1xxxx
UNALLOCATED
00x1
Data Processing -- Immediate
100x 1 0 0
Data-processing (1 source immediate)
11 111x
PC-rel. addressing
00xx
Add/subtract (immediate)
010x
Add/subtract (immediate, with tags)
0110
Min/max (immediate)
0111
Logical (immediate)
100x
Move wide (immediate)
101x
Bitfield
110x
Extract
!= 11 111x
Branches, Exception Generating and System instructions
101x 1 0 1
Conditional branch (immediate)
010 00xxxxxxxxxxxx
Miscellaneous branch (immediate)
010 01xxxxxxxxxxxx
Compare bytes/halfwords in registers and branch
011 00xxxxxxxx1xxx
UNALLOCATED
01x 1xxxxxxxxxxxxx
Exception generation
110 00xxxxxxxxxxxx
UNALLOCATED
110 010000000x00xx
UNALLOCATED
110 010000001000xx
UNALLOCATED
110 01000000110000
System instructions with register argument
110 01000000110001
Hints
110 01000000110010 11111
UNALLOCATED
110 01000000110010 != 11111
Barriers
110 01000000110011
UNALLOCATED
110 01000001xx00xx
PSTATE
110 0100000xxx0100
UNALLOCATED
110 0100000xxx0101
UNALLOCATED
110 0100000xxx011x
UNALLOCATED
110 0100000xxx1xxx
UNALLOCATED
110 0100100xxxxxxx
System instructions
110 0100x01xxxxxxx
System register move
110 0100x1xxxxxxxx
UNALLOCATED
110 0101x00xxxxxxx
System pair instructions
110 0101x01xxxxxxx
System register pair move
110 0101x1xxxxxxxx
UNALLOCATED
110 011xxxxxxxxxxx
Unconditional branch (register)
110 1xxxxxxxxxxxxx
UNALLOCATED
111 00xxxxxxxx1xxx
UNALLOCATED
111 1xxxxxxxxxxxxx
Unconditional branch (immediate)
x00
Compare and branch (immediate)
x01 0xxxxxxxxxxxxx
Test and branch (immediate)
x01 1xxxxxxxxxxxxx
Compare registers and branch
x11 00xxxxxxxx00xx
UNALLOCATED
x11 00xxxxxxxx01xx
Compare register with immediate and branch
x11 01xxxxxxxxx0xx
UNALLOCATED
x11 01xxxxxxxxx1xx
Data Processing -- Register
x101 1 0 1
Data-processing (2 source)
0 1 0110
Data-processing (1 source)
1 1 0110
Logical (shifted register)
0 0xxx
Add/subtract (shifted register)
0 1xx0
Add/subtract (extended register)
0 1xx1
Add/subtract (with carry)
1 0000 000000
Add/subtract (checked pointer)
1 0000 001xxx
UNALLOCATED
1 0000 011xxx
UNALLOCATED
1 0000 100000
UNALLOCATED
1 0000 1x1xxx
Rotate right into flags
1 0000 x00001
UNALLOCATED
1 0000 x0010x
UNALLOCATED
1 0000 x10x0x
Evaluate into flags
1 0000 xx0010
UNALLOCATED
1 0000 xx0011
UNALLOCATED
1 0000 xx011x
Conditional compare (register)
1 0010 xxxx0x
Conditional compare (immediate)
1 0010 xxxx1x
Conditional select
1 0100
UNALLOCATED
1 0xx1
Data-processing (3 source)
1 1xxx
Data Processing -- Scalar Floating-Point and Advanced SIMD
x111 1 1 1
UNALLOCATED
00x0 0x x101 00xxxxx10
UNALLOCATED
00x0 11 xxxxxxxx1
Cryptographic AES
0100 0x x101 00xxxxx10
Cryptographic three-register SHA
0101 0x x0xx xxx0xxx00
UNALLOCATED
0101 0x x0xx xxx0xxx10
UNALLOCATED
0101 0x x0xx xxx1xxxx0
Cryptographic two-register SHA
0101 0x x101 00xxxxx10
UNALLOCATED
0111 0x x0xx xxxxxxxx0
UNALLOCATED
011x 0x x101 00xxxxx10
Advanced SIMD scalar copy
01x1 00 00xx xxx0xxxx1
UNALLOCATED
01x1 01 00xx xxx0xxxx1
UNALLOCATED
01x1 0x 0111 00xxxxx10
Advanced SIMD scalar three same FP16
01x1 0x 10xx xxx00xxx1
UNALLOCATED
01x1 0x 10xx xxx01xxx1
Advanced SIMD scalar two-register miscellaneous FP16
01x1 0x 1111 00xxxxx10
Advanced SIMD scalar three same extra
01x1 0x x0xx xxx1xxxx1
Advanced SIMD scalar two-register miscellaneous
01x1 0x x100 00xxxxx10
Advanced SIMD scalar pairwise
01x1 0x x110 00xxxxx10
UNALLOCATED
01x1 0x x1xx 01xxxxx10
UNALLOCATED
01x1 0x x1xx 1xxxxxx10
Advanced SIMD scalar three different
01x1 0x x1xx xxxxxxx00
Advanced SIMD scalar three same
01x1 0x x1xx xxxxxxxx1
Advanced SIMD scalar shift by immediate
01x1 10 xxxxxxxx1
Advanced SIMD scalar x indexed element
01x1 1x xxxxxxxx0
UNALLOCATED
01xx 11 xxxxxxxx1
Advanced SIMD table lookup
0x00 0x x0xx xxx0xxx00
Advanced SIMD permute
0x00 0x x0xx xxx0xxx10
Advanced SIMD extract
0x10 0x x0xx xxx0xxxx0
Advanced SIMD copy
0xx0 00 00xx xxx0xxxx1
UNALLOCATED
0xx0 01 00xx xxx0xxxx1
UNALLOCATED
0xx0 0x 0111 00xxxxx10
Advanced SIMD three same (FP16)
0xx0 0x 10xx xxx00xxx1
UNALLOCATED
0xx0 0x 10xx xxx01xxx1
Advanced SIMD two-register miscellaneous (FP16)
0xx0 0x 1111 00xxxxx10
UNALLOCATED
0xx0 0x x0xx xxx1xxxx0
Advanced SIMD three-register extension
0xx0 0x x0xx xxx1xxxx1
Advanced SIMD two-register miscellaneous
0xx0 0x x100 00xxxxx10
Advanced SIMD across lanes
0xx0 0x x110 00xxxxx10
UNALLOCATED
0xx0 0x x1xx 01xxxxx10
UNALLOCATED
0xx0 0x x1xx 1xxxxxx10
Advanced SIMD three different
0xx0 0x x1xx xxxxxxx00
Advanced SIMD three same
0xx0 0x x1xx xxxxxxxx1
Advanced SIMD modified immediate
0xx0 10 0000 xxxxxxxx1
Advanced SIMD shift by immediate
0xx0 10 != 0000 xxxxxxxx1
Advanced SIMD vector x indexed element
0xx0 1x xxxxxxxx0
UNALLOCATED
10x0
UNALLOCATED
1100 00 0xxx xxx1xxxxx
Cryptographic three-register, imm2
1100 00 10xx xxx10xxxx
UNALLOCATED
1100 00 10xx xxx11xxxx
Cryptographic three-register SHA 512
1100 00 11xx xxx1x00xx
UNALLOCATED
1100 00 11xx xxx1x01xx
UNALLOCATED
1100 00 11xx xxx1x1xxx
Cryptographic four-register
1100 00 xxx0xxxxx
Cryptographic three-register, imm6
1100 01 00xx
UNALLOCATED
1100 01 1000 0000xxxxx
Cryptographic two-register SHA 512
1100 01 1000 0001000xx
UNALLOCATED
1100 01 1000 0001100xx
UNALLOCATED
1100 01 1000 0001x01xx
UNALLOCATED
1100 01 1000 0001x1xxx
UNALLOCATED
1100 01 1000 001xxxxxx
UNALLOCATED
1100 01 1000 01xxxxxxx
UNALLOCATED
1100 01 1000 1xxxxxxxx
UNALLOCATED
1100 01 1001
UNALLOCATED
1100 01 101x
UNALLOCATED
1100 01 x1xx
UNALLOCATED
1100 1x
UNALLOCATED
1110
UNALLOCATED
11x1
Conversion between floating-point and fixed-point
x0x1 0x x0xx
Conversion between floating-point and integer
x0x1 0x x1xx xxx000000
UNALLOCATED
x0x1 0x x1xx xxx100000
Floating-point data-processing (1 source)
x0x1 0x x1xx xxxx10000
Floating-point compare
x0x1 0x x1xx xxxxx1000
Floating-point immediate
x0x1 0x x1xx xxxxxx100
Floating-point conditional compare
x0x1 0x x1xx xxxxxxx01
Floating-point data-processing (2 source)
x0x1 0x x1xx xxxxxxx10
Floating-point conditional select
x0x1 0x x1xx xxxxxxx11
Floating-point data-processing (3 source)
x0x1 1x
Loads and Stores
x1x0 1 0
UNALLOCATED
0000 0 1xx1xxxxxxxxxxx
UNALLOCATED
0001 1 1xx1xxxxxxxxxxx
Compare and swap pair
0x00 0 00x1xxxxxxxxxxx
UNALLOCATED
0x00 0 10x0xxxxxxxxxxx
Compare and swap pair (unprivileged)
0x00 0 11x0xxxxxxxxxxx
Advanced SIMD load/store multiple structures
0x00 1 00x000000xxxxxx
UNALLOCATED
0x00 1 00x000001xxxxxx
Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 01x0xxxxxxxxxxx
UNALLOCATED
0x00 1 0xx1xxxxxxxxxxx
UNALLOCATED
0x00 1 10x10001xxxxxxx
UNALLOCATED
0x00 1 10x1001xxxxxxxx
UNALLOCATED
0x00 1 10x101xxxxxxxxx
UNALLOCATED
0x00 1 10x11xxxxxxxxxx
Advanced SIMD load/store single structure
0x00 1 10xx0000xxxxxxx
Advanced SIMD load/store single structure (post-indexed)
0x00 1 11xxxxxxxxxxxxx
UNALLOCATED
0x00 1 x0x00001xxxxxxx
UNALLOCATED
0x00 1 x0x0001xxxxxxxx
UNALLOCATED
0x00 1 x0x001xxxxxxxxx
UNALLOCATED
0x00 1 x0x01xxxxxxxxxx
UNALLOCATED
0x01 0 1xx0xxxxxxxxx11
RCW compare and swap
0x01 0 1xx1xxxxx000010
RCW compare and swap pair
0x01 0 1xx1xxxxx000011
UNALLOCATED
0x01 0 1xx1xxxxx00011x
UNALLOCATED
0x01 0 1xx1xxxxx001x1x
UNALLOCATED
0x01 0 1xx1xxxxx01xx1x
UNALLOCATED
0x01 0 1xx1xxxxx1xxx1x
128-bit atomic memory operations
0x01 0 1xx1xxxxxxxxx00
Atomic memory operations (unprivileged)
0x01 0 1xx1xxxxxxxxx01
UNALLOCATED
1001 0 1xx0xxxxxxxxx11
UNALLOCATED
1001 1 1xx1xxxxxxxxxxx
UNALLOCATED
100x 0 1xx1xxxxxxxxxxx
GCS load/store
1101 0 1000111110xxx11
UNALLOCATED
1101 0 1100111110xxx11
UNALLOCATED
1101 0 1x000xxxxxxxx11
UNALLOCATED
1101 0 1x0010xxxxxxx11
UNALLOCATED
1101 0 1x00110xxxxxx11
UNALLOCATED
1101 0 1x001110xxxxx11
UNALLOCATED
1101 0 1x0011110xxxx11
UNALLOCATED
1101 0 1x00111111xxx11
UNALLOCATED
1101 0 1x10xxxxxxxxx11
Load/store memory tags
1101 0 1xx1xxxxxxxxxxx
Load/store exclusive pair
1x00 0 00x1xxxxxxxxxxx
Load/store exclusive register (unprivileged)
1x00 0 10x0xxxxxxxxxxx
Compare and swap (unprivileged)
1x00 0 11x0xxxxxxxxxxx
UNALLOCATED
1x00 1
UNALLOCATED
x100 0 1xx1xxxxxxxxxxx
UNALLOCATED
x101 1 1xx1xxxxxxxxxxx
Load/store exclusive register
xx00 0 00x0xxxxxxxxxxx
Load/store ordered
xx00 0 01x0xxxxxxxxxxx
Compare and swap
xx00 0 01x1xxxxxxxxxxx
Load/store ordered register pair
xx01 0 10x0xxxxxxxxx10
Load/store ordered (writeback)
xx01 0 11x000000000010
UNALLOCATED
xx01 0 11x000000000110
UNALLOCATED
xx01 0 11x000000001x10
UNALLOCATED
xx01 0 11x00000001xx10
UNALLOCATED
xx01 0 11x0000001xxx10
UNALLOCATED
xx01 0 11x000001xxxx10
UNALLOCATED
xx01 0 11x00001xxxxx10
UNALLOCATED
xx01 0 11x0001xxxxxx10
UNALLOCATED
xx01 0 11x001xxxxxxx10
UNALLOCATED
xx01 0 11x01xxxxxxxx10
Load/store ordered (unscaled immediate)
xx01 0 1xx0xxxxxxxxx00
UNALLOCATED
xx01 1 1xx0xxxxxxxxx00
Load/store ordered (SIMD&FP)
xx01 1 1xx0xxxxxxxxx10
UNALLOCATED
xx01 1 1xx0xxxxxxxxx11
Load register (literal)
xx01 0xxxxxxxxxxxxxx
Memory Copy and Memory Set
xx01 1xx0xxxxxxxxx01
Load/store no-allocate pair (offset)
xx10 00xxxxxxxxxxxxx
Load/store register pair (post-indexed)
xx10 01xxxxxxxxxxxxx
Load/store register pair (offset)
xx10 10xxxxxxxxxxxxx
Load/store register pair (pre-indexed)
xx10 11xxxxxxxxxxxxx
Load/store register (unscaled immediate)
xx11 0xx0xxxxxxxxx00
Load/store register (immediate post-indexed)
xx11 0xx0xxxxxxxxx01
Load/store register (unprivileged)
xx11 0xx0xxxxxxxxx10
Load/store register (immediate pre-indexed)
xx11 0xx0xxxxxxxxx11
Atomic memory operations
xx11 0xx1xxxxxxxxx00
Load/store register (register offset)
xx11 0xx1xxxxxxxxx10
Load/store register (pac)
xx11 0xx1xxxxxxxxxx1
Load/store register (unsigned immediate)
xx11 1xxxxxxxxxxxxxx Instruction bits Encoding Group 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Loads and Stores 1 0 1 Data Processing -- Register 1 1 1 Data Processing -- Scalar Floating-Point and Advanced SIMD 1 0 0 Data Processing -- Immediate 1 0 1 Branches, Exception Generating and System instructions 0 0 0 0 0 Reserved 1 0 0 0 0 SME encodings 0 0 1 0 SVE encodings Instruction bits Instruction class 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0xx0xxxx 1 SVE Integer Multiply-Add - Predicated 0 0 0 0 0 1 0 0 0 000xxx SVE Integer Binary Arithmetic - Predicated 0 0 0 0 0 1 0 0 0 001xxx SVE Integer Reduction 0 0 0 0 0 1 0 0 0 100xxx SVE Bitwise Shift - Predicated 0 0 0 0 0 1 0 0 0 101xxx SVE Integer Unary Arithmetic - Predicated 000 0 0 1 0 0xx1xxxx 000xxx SVE Integer Arithmetic - Unpredicated 0 0 0 0 0 1 0 0xx1xxxx 0 0 1 SVE Bitwise Logical - Unpredicated 0 0 0 0 0 1 0 0 1 0 1 0 0 SVE Index Generation 0 0 0 0 0 1 0 0 1 0 1 0 1 SVE Stack Allocation 0 0 0 0 0 1 0 0xx1xxxx 0 1 1 SVE2 Integer Arithmetic - Unpredicated 0 0 0 0 0 1 0 0xx1xxxx 1 0 0 SVE Bitwise Shift - Unpredicated 000 0 0 1 0 0xx1xxxx 1010xx SVE Address Generation 0 0 0 0 0 1 0 0xx1xxxx 1 0 1 1 SVE Integer Misc - Unpredicated 0 0 0 0 0 1 0 0 1 1 1 SVE Element Count 0 0 0 0 0 1 0 1 0 0 SVE Bitwise Immediate 0 0 0 0 0 1 0 1xx01xxx SVE Integer Wide Immediate - Predicated 000 0 0 1 0 1xx1xxxx 001000 SVE Permute Vector - Indexed DUP 0 0 0 0 0 1 0 1 1 001001 SVE Permute Vector - One Source Quadwords 000 0 0 1 0 1xx1xxxx 00101x SVE Permute Vector - Three Sources TBL 000 0 0 1 0 1xx1xxxx 001100 SVE Permute Vector - Two Sources TBL 000 0 0 1 0 1xx1xxxx 001101 SVE Permute Vector - TBXQ 0 0 0 0 0 1 0 1 1 0 0 1 1 1 0 SVE Permute Vector - Unpredicated 0 0 0 0 0 1 0 1 1 0 1 0 SVE Permute Predicate 000 0 0 1 0 1xx1xxxx 011xxx SVE Permute Vector - Interleaving 0 0 0 0 0 1 0 1 1 1 0 SVE Permute Vector - Predicated 000 0 0 1 0 1xx1xxxx 11xxxx SVE Vector Select 0 0 0 0 0 1 0 1 0 1 000xxx SVE Permute Vector - Extract 0 0 0 0 0 1 0 1 1 1 000xxx SVE Permute Vector - Segments 0 0 1 0 0 1 0 0xx0xxxx SVE Integer Compare - Vectors 001 0 0 1 0 0xx1xxxx SVE Integer Compare - Unsigned Immediate 001 0 0 1 0 1xx0xxxx x0xxxx SVE Integer Compare - Signed Immediate 001 0 0 1 0 1xx00xxx 01xxxx SVE Predicate Logical Operations 0 0 1 0 0 1 0 1xx00xxx 11xxxx SVE Propagate Break 0 0 1 0 0 1 0 1 0 1 0 1 SVE Partition Break 0 0 1 0 0 1 0 1 0 1 1 1 SVE Predicate Misc 0 0 1 0 0 1 0 1 1 0 0 SVE Integer Compare - Scalars 001 0 0 1 0 1xx1xxxx 01xxxx 0 SVE Predicate Select 0 0 1 0 0 1 0 1 1 0 1 1 SVE Scalar Integer Compare - Predicate-as-counter 0 0 1 0 0 1 0 1 1 11xxxx SVE Integer Wide Immediate - Unpredicated 0 0 1 0 0 1 0 1 1 0 0 1 0 SVE Predicate Count 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 SVE Inc/Dec by Predicate Count 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 SVE Write FFR 0 1 0 0 0 1 0 0xx0xxxx 0 SVE Integer Multiply-Add - Unpredicated 0 1 0 0 0 1 0 0 0 1 0 SVE2 Integer - Predicated 010 0 0 1 0 0xx0xxxx 11000x SVE integer clamp 0 1 0 0 0 1 0 0 0 1 1 0 1 0 SVE2 multiply-add (checked pointer) 010 0 0 1 0 0xx0xxxx 111xxx SVE Permute Vector - Two Sources Quadwords 0 1 0 0 0 1 0 0xx1xxxx SVE Multiply - Indexed 010 0 0 1 0 0000xxxx 11001x SVE two-way dot product 010 0 0 1 0 0 1 0 0 11001x SVE two-way dot product (indexed) 0 1 0 0 0 1 0 1xx0xxxx 0 SVE2 Widening Integer Arithmetic 0 1 0 0 0 1 0 1 0 1 0 SVE Misc 0 1 0 0 0 1 0 1 0 1 1 SVE2 Accumulate 0 1 0 0 0 1 0 1 1 0 SVE2 Narrowing 010 0 0 1 0 1xx1xxxx 100xxx SVE2 String Processing 0 1 0 0 0 1 0 1 1 1 0 1 SVE2 Histogram Computation (Segment) and Lookup Table 010 0 0 1 0 1xx1xxxx 110xxx SVE2 histogram generation (vector) 0 1 0 0 0 1 0 1 1 1 1 1 SVE2 Crypto Extensions 011 0 0 1 0 0xx0xxxx 0xxxxx SVE floating-point complex multiply-add (predicated) 011 0 0 1 0 0 0 0 0 0 101xxx SVE floating-point convert (top, predicated) 011 0 0 1 0 0xx00000 100xxx SVE floating-point complex add (predicated) 011 0 0 1 0 0 0 0 1 0 101xxx SVE floating-point convert precision odd elements 011 0 0 1 0 0 0 1 0 100xxx SVE2 floating-point pairwise operations 011 0 0 1 0 0xx010xx 101xxx SVE floating-point fast reduction - quadwords 0 1 1 0 0 1 0 0 0 1 1 1xxxxx SVE2 floating-point unary operations - zeroing predicated 011 0 0 1 0 0 1 0 0 0 0 SVE floating-point multiply-add (indexed) 011 0 0 1 0 0 1 0001xx SVE floating-point complex multiply-add (indexed) 011 0 0 1 0 0 1 0 0 1 0 0 SVE floating-point multiply (indexed) 011 0 0 1 0 0xx1xxxx 001001 SVE FP clamp 0 1 1 0 0 1 0 0 1 0 1 0 SVE floating-point widening multiply-add - indexed 0 1 1 0 0 1 0 0 1 1 0 0 0 SVE floating-point widening multiply-add 011 0 0 1 0 0xx1xxxx 1100xx SVE2 FP8 4x widening multiply-add - indexed 011 0 0 1 0 0 1 111001 SVE floating-point matrix multiply accumulate 011 0 0 1 0 0x01xxxx 0101xx SVE2 FP8 2x widening multiply-add - indexed 0 1 1 0 0 1 0 0 0 1 1 0 1 0 SVE2 FP8 widening multiply-add 011 0 0 1 0 0 0 1 111000 SVE2 FP8 matrix multiply-accumulate 011 0 0 1 0 1xx0xxxx x1xxxx SVE floating-point compare - vectors 011 0 0 1 0 1xx0xxxx 000xxx SVE floating-point arithmetic - unpredicated 0 1 1 0 0 1 0 1 0 1 0 0 SVE floating-point arithmetic - predicated 0 1 1 0 0 1 0 1 0 101xxx SVE floating-point unary operations - merging predicated 011 0 0 1 0 1xx000xx 001xxx SVE floating-point fast reduction 0 1 1 0 0 1 0 1 0 0 1 0 0 1 1 SVE floating-point unary operations - unpredicated 0 1 1 0 0 1 0 1 0 1 0 001xxx SVE floating-point compare - with zero 0 1 1 0 0 1 0 1 0 1 1 001xxx SVE floating-point accumulating reduction 0 1 1 0 0 1 0 1xx1xxxx SVE floating-point multiply-add 1 0 0 0 0 1 0 SVE Memory - 32-bit Gather and Unsized Contiguous 1 0 1 0 0 1 0 SVE Memory - Contiguous Load 1 1 0 0 0 1 0 SVE Memory - 64-bit Gather 1 1 1 0 0 1 0 0 0 SVE Memory - Contiguous Store and Unsized Contiguous 1 1 1 0 0 1 0 001xxx SVE Memory - Non-temporal and Quadword Scatter Store 1 1 1 0 0 1 0 011xxx SVE Memory - Non-temporal and Multi-register Contiguous Store 1 1 1 0 0 1 0 1x0xxx SVE Memory - Scatter with Optional Sign Extend 1 1 1 0 0 1 0 101xxx SVE Memory - Scatter 1 1 1 0 0 1 0 111xxx SVE Memory - Contiguous Store with Immediate Offset 1 0 0 0 0 0 1 1 0 SME Outer Product - 64 bit 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 SME2 Quarter Tile Outer Product - 64-bit 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SME2 Quarter Tile Outer Product - 16-bit and 32-bit 1 0 0 0 0 0 0 0 1 0 0 SME2 Sparse Outer Product 1 0 0 0 0 0 0 1 0 0 0 SME FP Outer Product - 32 bit 1 0 0 0 0 0 0 1 0 1 0 SME2 Outer Product - Misc 1 0 1 0 0 0 0 1 0 0 SME Integer Outer Product - 32 bit 1 0 1 0 0 0 0 0 0 SME2 Multi-vector - Memory (Contiguous) 1 0 1 0 0 0 0 1 0 SME2 Multi-vector - Memory (Strided) 1 1 0 0 0 0 0 0 0 0 0 0 0 SME Move into Array 1 1 0 0 0 0 0 0 0 0 0 1 SME Move from Array 1 1 0 0 0 0 0 0 0 1 0 0 SME Add Vector to Array 1 1 0 0 0 0 0 0 0 0 0 0 1 0 SME zero array 1 1 0 0 0 0 0 0 0 0 0 0 1 1 SME2 Multiple Zero 1 1 0 0 0 0 0 0 0 1 0 0 1 0 SME2 zero lookup table 1 1 0 0 0 0 0 0 0 1 0 0 1 1 SME2 Move Lookup Table 1 1 0 0 0 0 0 0 1 0 0 1 SME2 Expand Lookup Table (Contiguous) 1 1 0 0 0 0 0 0 1 0 0 1 1 SME2 Expand Lookup Table (Non-contiguous) 1 1 0 0 0 0 0 1 0 0 SME2 Multi-vector - Indexed (One register) 1 1 0 0 0 0 0 1 0 1 0 SME2 Multi-vector - Indexed (Two registers) 1 1 0 0 0 0 0 1 0 1 1 SME2 Multi-vector - Indexed (Four registers) 1 1 0 0 0 0 0 1 1 1 0 0 SME2 Multi-vector - SVE Select 1 1 0 0 0 0 0 1 1 1 1 0 SME2 Multi-vector - SVE Constructive Binary 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 SME2 Multi-vector - SVE Constructive Unary 1 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 SME2 Multi-vector - FP Multiply 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 SME2 Multiple and Single Vector - FP multiply 1 1 0 0 0 0 0 1xx1xxxx0101100 SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers) 1 1 0 0 0 0 0 1xx1xxxx0101101 SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers) 1 1 0 0 0 0 0 1xx1xxx00101110 xxxx0x SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers) 1 1 0 0 0 0 0 1xx1xxx00101111 0 SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers) 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers) 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers) 1 1 0 0 0 0 0 1 0 1 0 0 SME2 Multi-vector - Multiple and Single Array Vectors (Two registers) 1 1 0 0 0 0 0 1 0 1 1 0 SME2 Multi-vector - Multiple and Single Array Vectors (Four registers) 1 1 0 0 0 0 0 1 1 1 0 0 SME2 Multi-vector - Multiple Array Vectors (Two registers) 1 1 0 0 0 0 0 1 1 1 1 0 SME2 Multi-vector - Multiple Array Vectors (Four registers) 1 1 1 0 0 0 0 SME Memory 0 00 0 0 0 0 000000000 Reserved 1 0 0 0 0 PC-rel. addressing 1 0 0 0 1 0 Add/subtract (immediate) 1 0 0 0110 Add/subtract (immediate, with tags) 1 0 0 0111 Min/max (immediate) 1 0 0 1 0 0 Logical (immediate) 1 0 0 1 0 1 Move wide (immediate) 1 0 0 1 1 0 Bitfield 11 1 0 0 1 1 1 Data-processing (1 source immediate) != 11 1 0 0 1 1 1 Extract 0 0 1 0 1 Unconditional branch (immediate) 0 1 1 0 1 0 Compare and branch (immediate) 0 1 1 0 1 1 Test and branch (immediate) 1 1 1 0 1 0 0 0 0 Compare registers and branch 1 1 1 0 1 0 1 0 Compare register with immediate and branch 010 1 0 1 0 0 Conditional branch (immediate) 010 1 0 1 0 1 Miscellaneous branch (immediate) 011 1 0 1 0 0 1 Compare bytes/halfwords in registers and branch 110 1 0 1 0 0 Exception generation 110 1 0 1 0 1 0 0 0 1 System instructions 110 1 0 1 0 1 0 0 1 System register move 110 1 0 1 0 1 0 0 0 0 0 0 1 0 0 PSTATE 110 1 0 1 01000000110001 System instructions with register argument 110 1 0 1 01000000110010 1 1 1 1 1 Hints 110 1 0 1 01000000110011 Barriers 110 1 0 1 0 1 0 1 0 1 System pair instructions 110 1 0 1 0 1 0 1 1 System register pair move 110 1 0 1 1 Unconditional branch (register) 0 0 1 0 0 0 0 0 Load/store exclusive register 0 0 1 0 0 0 1 0 Load/store ordered 0 0 1 0 0 0 1 1 Compare and swap 0 1 1 0 0 Load register (literal) 0 1 1 0 1 0 0 1 Memory Copy and Memory Set 0 1 1 0 0 1 0 0 0 Load/store ordered (unscaled immediate) 0 1 1 0 0 1 0 0 1 0 Load/store ordered register pair 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Load/store ordered (writeback) 0 1 1 1 0 1 0 1 0 Load/store ordered (SIMD&FP) 1 0 1 0 0 0 Load/store no-allocate pair (offset) 1 0 1 0 0 1 Load/store register pair (post-indexed) 1 0 1 0 1 0 Load/store register pair (offset) 1 0 1 0 1 1 Load/store register pair (pre-indexed) 1 1 1 0 0 0 0 0 Load/store register (unscaled immediate) 1 1 1 0 0 0 0 1 Load/store register (immediate post-indexed) 1 1 1 0 0 0 1 0 Load/store register (unprivileged) 1 1 1 0 0 0 1 1 Load/store register (immediate pre-indexed) 1 1 1 0 0 1 1 Load/store register (pac) 1 1 1 0 0 1 0 0 Atomic memory operations 1 1 1 0 0 1 1 0 Load/store register (register offset) 1 1 1 0 1 Load/store register (unsigned immediate) 0 0 0 1 0 0 0 0 1 Compare and swap pair 0 0 0 1 0 0 1 1 0 Compare and swap pair (unprivileged) 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Advanced SIMD load/store multiple structures 0 0 0 1 1 0 0 1 0 Advanced SIMD load/store multiple structures (post-indexed) 0 0 0 1 1 0 1 0 0 0 0 0 Advanced SIMD load/store single structure 0 0 0 1 1 0 1 1 Advanced SIMD load/store single structure (post-indexed) 0 0 1 1 0 0 1 1 0 0 128-bit atomic memory operations 0 0 1 1 0 0 1 1 0 1 Atomic memory operations (unprivileged) 0 0 1 1 0 0 1 1 0 0 0 0 1 0 RCW compare and swap 0 0 1 1 0 0 1 1 0 0 0 0 1 1 RCW compare and swap pair 1 0 0 1 0 0 0 0 1 Load/store exclusive pair 1 0 0 1 0 0 1 0 0 Load/store exclusive register (unprivileged) 1 0 0 1 0 0 1 1 0 Compare and swap (unprivileged) 1101 1 0 0 1 1 Load/store memory tags 1101 1 0 0 1 0 0 0 1 1 1 1 1 0 1 1 GCS load/store 0 1 0 1 0 Logical (shifted register) 0 1 0 1 1 0 Add/subtract (shifted register) 0 1 0 1 1 1 Add/subtract (extended register) 1 1 0 1 0000 0 0 1 0 Evaluate into flags 1 1 0 1 0000 0 0 0 0 1 Rotate right into flags 1 1 0 1 0000 000000 Add/subtract (with carry) 1 1 0 1 0000 0 0 1 Add/subtract (checked pointer) 1 1 0 1 0010 0 Conditional compare (register) 1 1 0 1 0010 1 Conditional compare (immediate) 1 1 0 1 0 1 0 0 Conditional select 1 1 0 1 1 Data-processing (3 source) 0 1 1 0 1 0110 Data-processing (2 source) 1 1 1 0 1 0110 Data-processing (1 source) 0 1 1 1 1 0 0 Conversion between floating-point and fixed-point 0 1 1 1 1 0 1 0 1 Floating-point conditional compare 0 1 1 1 1 0 1 1 0 Floating-point data-processing (2 source) 0 1 1 1 1 0 1 1 1 Floating-point conditional select 0 1 1 1 1 0 1 1 0 0 Floating-point immediate 0 1 1 1 1 0 1 1 0 0 0 Floating-point compare 0 1 1 1 1 0 1 1 0 0 0 0 Floating-point data-processing (1 source) 0 1 1 1 1 0 1 0 0 0 0 0 0 Conversion between floating-point and integer 0 1 1 1 1 1 Floating-point data-processing (3 source) 0 0 1 1 1 0 0 1 1 Advanced SIMD three-register extension 0 0 1 1 1 0 1 1 Advanced SIMD three same 0 0 1 1 1 0 1 0 0 Advanced SIMD three different 0 0 1 1 1 0 1 0 0 0 0 1 0 Advanced SIMD two-register miscellaneous 0 0 1 1 1 0 1 1 0 0 0 1 0 Advanced SIMD across lanes 0 0 1 1 1 0 1 0 0 0 1 Advanced SIMD three same (FP16) 0 0 1 1 1 0 1111 0 0 1 0 Advanced SIMD two-register miscellaneous (FP16) 0 0 1 1 1 00 0 0 0 1 Advanced SIMD copy 0 0 1 1 1 1 0 Advanced SIMD vector x indexed element 0 0 1 1 1 10 0000 1 Advanced SIMD modified immediate 0 0 1 1 1 10 != 0000 1 Advanced SIMD shift by immediate 0 0 0 1 1 1 0 0 0 0 0 Advanced SIMD table lookup 0 0 0 1 1 1 0 0 0 1 0 Advanced SIMD permute 0 1 0 1 1 1 0 0 0 0 Advanced SIMD extract 0 1 1 1 1 1 0 0 1 1 Advanced SIMD scalar three same extra 0 1 1 1 1 1 0 1 1 Advanced SIMD scalar three same 0 1 1 1 1 1 0 1 0 0 Advanced SIMD scalar three different 0 1 1 1 1 1 0 1 0 0 0 0 1 0 Advanced SIMD scalar two-register miscellaneous 0 1 1 1 1 1 0 1 1 0 0 0 1 0 Advanced SIMD scalar pairwise 0 1 1 1 1 1 0 1 0 0 0 1 Advanced SIMD scalar three same FP16 0 1 1 1 1 1 0 1111 0 0 1 0 Advanced SIMD scalar two-register miscellaneous FP16 0 1 1 1 1 1 00 0 0 0 1 Advanced SIMD scalar copy 0 1 1 1 1 1 1 0 Advanced SIMD scalar x indexed element 0 1 1 1 1 1 10 1 Advanced SIMD scalar shift by immediate 0100 1 1 1 0 1 0 1 0 0 1 0 Cryptographic AES 0101 1 1 1 0 0 0 0 0 Cryptographic three-register SHA 0101 1 1 1 0 1 0 1 0 0 1 0 Cryptographic two-register SHA 1100 1 1 1 00 0 Cryptographic four-register 1100 1 1 1 00 1 0 1 0 Cryptographic three-register, imm2 1100 1 1 1 00 1 1 1 0 0 Cryptographic three-register SHA 512 1100 1 1 1 01 0 0 Cryptographic three-register, imm6 1100 1 1 1 01 1000 0 0 0 1 0 0 0 Cryptographic two-register SHA 512 Branches, Exception Generating and System instructions 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 1 Decode fields Instruction page Encoding CRm op2 Rt != 11111 UNALLOCATED 000 11111 UNALLOCATED 010 11111 CLREX 100 11111 DSB Memory barrier 101 11111 DMB 110 11111 ISB 111 11111 SB xx0x 0x1 11111 UNALLOCATED xx10 001 11111 DSB Memory nXS barrier xx10 011 11111 UNALLOCATED xx11 0x1 11111 UNALLOCATED 0 1 1 0 1 0 Decode fields Instruction page Encoding sf op 0 0 CBZ 32-bit 0 1 CBNZ 32-bit 1 0 CBZ 64-bit 1 1 CBNZ 64-bit 0 1 1 1 0 1 0 0 1 Decode fields Instruction page Encoding cc H 000 0 CBB<cc> Greater than 000 1 CBH<cc> Greater than 001 0 CBB<cc> Greater than or equal 001 1 CBH<cc> Greater than or equal 010 0 CBB<cc> Higher 010 1 CBH<cc> Higher 011 0 CBB<cc> Higher or same 011 1 CBH<cc> Higher or same 10x UNALLOCATED 110 0 CBB<cc> Equal 110 1 CBH<cc> Equal 111 0 CBB<cc> Not equal 111 1 CBH<cc> Not equal 1 1 1 0 1 0 1 0 Decode fields Instruction page Encoding sf cc 10x UNALLOCATED 0 000 CB<cc> (immediate) 32-bit greater than 0 001 CB<cc> (immediate) 32-bit less than 0 010 CB<cc> (immediate) 32-bit higher 0 011 CB<cc> (immediate) 32-bit lower 0 110 CB<cc> (immediate) 32-bit equal 0 111 CB<cc> (immediate) 32-bit not equal 1 000 CB<cc> (immediate) 64-bit greater than 1 001 CB<cc> (immediate) 64-bit less than 1 010 CB<cc> (immediate) 64-bit higher 1 011 CB<cc> (immediate) 64-bit lower 1 110 CB<cc> (immediate) 64-bit equal 1 111 CB<cc> (immediate) 64-bit not equal 1 1 1 0 1 0 0 0 0 Decode fields Instruction page Encoding sf cc 10x UNALLOCATED 0 000 CB<cc> (register) 32-bit greater than 0 001 CB<cc> (register) 32-bit greater than or equal 0 010 CB<cc> (register) 32-bit higher 0 011 CB<cc> (register) 32-bit higher or same 0 110 CB<cc> (register) 32-bit equal 0 111 CB<cc> (register) 32-bit not equal 1 000 CB<cc> (register) 64-bit greater than 1 001 CB<cc> (register) 64-bit greater than or equal 1 010 CB<cc> (register) 64-bit higher 1 011 CB<cc> (register) 64-bit higher or same 1 110 CB<cc> (register) 64-bit equal 1 111 CB<cc> (register) 64-bit not equal 0 1 0 1 0 1 0 0 Decode fields Instruction page Encoding o0 0 B.cond 1 BC.cond 1 1 0 1 0 1 0 0 Decode fields Instruction page Encoding opc op2 LL != 000 UNALLOCATED x11 000 UNALLOCATED 000 000 00 UNALLOCATED 000 000 01 SVC 000 000 10 HVC 000 000 11 SMC 001 000 00 BRK 001 000 != 00 UNALLOCATED 010 000 00 HLT 010 000 != 00 UNALLOCATED 1x0 000 UNALLOCATED 101 000 00 UNALLOCATED 101 000 01 DCPS1 101 000 10 DCPS2 101 000 11 DCPS3 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1 Decode fields Instruction page Encoding CRm op2 HINT 0000 000 NOP 0000 001 YIELD 0000 010 WFE 0000 011 WFI 0000 100 SEV 0000 101 SEVL 0000 110 DGH 0000 111 XPACD, XPACI, XPACLRI System 0001 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA PACIA1716 0001 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB PACIB1716 0001 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA AUTIA1716 0001 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB AUTIB1716 0010 000 ESB 0010 001 PSB 0010 010 TSB 0010 011 GCSB 0010 100 CSDB 0010 110 CLRBHB 0011 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA PACIAZ 0011 001 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA PACIASP 0011 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB PACIBZ 0011 011 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB PACIBSP 0011 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA AUTIAZ 0011 101 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA AUTIASP 0011 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB AUTIBZ 0011 111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB AUTIBSP 0100 xx0 BTI 0100 111 PACM 0101 000 CHKFEAT 0110 00x STSHH 0 1 0 1 0 1 0 1 Decode fields Instruction page Encoding opc op2 00x != 11111 UNALLOCATED 000 11111 RETAASPPC, RETABSPPC RETAASPPC 001 11111 RETAASPPC, RETABSPPC RETABSPPC 01x UNALLOCATED 1xx UNALLOCATED 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 Decode fields Instruction page Encoding op1:op2 Rt 0xxxx UNALLOCATED 10xxx UNALLOCATED 110xx UNALLOCATED 1110x UNALLOCATED 11110 UNALLOCATED 000000 11111 CFINV 000001 11111 XAFLAG 000010 11111 AXFLAG != 00000x 11111 MSR (immediate) 1 1 0 1 0 1 0 1 0 0 0 1 Decode fields Instruction page Encoding L 0 SYS 1 SYSL 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 Decode fields Instruction page Encoding CRm op2 0000 000 WFET 0000 001 WFIT 0000 01x UNALLOCATED 0000 1xx UNALLOCATED != 0000 UNALLOCATED 1 1 0 1 0 1 0 1 0 1 0 1 Decode fields Instruction page Encoding L 0 SYSP 1 UNALLOCATED 1 1 0 1 0 1 0 1 0 0 1 Decode fields Instruction page Encoding L 0 MSR (register) 1 MRS 1 1 0 1 0 1 0 1 0 1 1 Decode fields Instruction page Encoding L 0 MSRR 1 MRRS 0 1 1 0 1 1 Decode fields Instruction page Encoding op 0 TBZ 1 TBNZ 0 0 1 0 1 Decode fields Instruction page Encoding op 0 B 1 BL 1 1 0 1 0 1 1 Decode fields Instruction page Encoding opc op2 op3 Rn op4 11111 0001xx UNALLOCATED 11111 001xxx UNALLOCATED 11111 01xxxx UNALLOCATED 11111 1xxxxx UNALLOCATED != 11111 UNALLOCATED 00x0 11111 000000 != 00000 UNALLOCATED 00x0 11111 000001 UNALLOCATED 000x 11111 00001x != 11111 UNALLOCATED 0000 11111 000000 00000 BR 0000 11111 000010 11111 BRAA, BRAAZ, BRAB, BRABZ Key A, zero modifier 0000 11111 000011 11111 BRAA, BRAAZ, BRAB, BRABZ Key B, zero modifier 0001 11111 000000 00000 BLR 0001 11111 000000 != 00000 UNALLOCATED 0001 11111 000001 UNALLOCATED 0001 11111 000010 11111 BLRAA, BLRAAZ, BLRAB, BLRABZ Key A, zero modifier 0001 11111 000011 11111 BLRAA, BLRAAZ, BLRAB, BLRABZ Key B, zero modifier 0010 11111 000000 00000 RET 0010 11111 00001x != 11111 UNALLOCATED 0010 11111 000010 11111 11111 RETAA, RETAB RETAA 0010 11111 000010 11111 != 11111 RETAASPPCR, RETABSPPCR RETAASPPCR 0010 11111 000011 11111 11111 RETAA, RETAB RETAB 0010 11111 000011 11111 != 11111 RETAASPPCR, RETABSPPCR RETABSPPCR 0011 11111 0000xx UNALLOCATED 010x 11111 0000xx != 11111 UNALLOCATED 010x 11111 000000 11111 != 00000 UNALLOCATED 010x 11111 000001 11111 UNALLOCATED 010x 11111 00001x 11111 xxxx0 UNALLOCATED 0100 11111 000000 11111 00000 ERET 0100 11111 00001x 11111 0xxx1 UNALLOCATED 0100 11111 00001x 11111 10xx1 UNALLOCATED 0100 11111 00001x 11111 110x1 UNALLOCATED 0100 11111 00001x 11111 11101 UNALLOCATED 0100 11111 000010 11111 11111 ERETAA, ERETAB ERETAA 0100 11111 000011 11111 11111 ERETAA, ERETAB ERETAB 0101 11111 000000 11111 00000 DRPS 0101 11111 00001x 11111 xxxx1 UNALLOCATED 011x 11111 0000xx UNALLOCATED 100x 11111 00000x UNALLOCATED 1000 11111 000010 BRAA, BRAAZ, BRAB, BRABZ Key A, register modifier 1000 11111 000011 BRAA, BRAAZ, BRAB, BRABZ Key B, register modifier 1001 11111 000010 BLRAA, BLRAAZ, BLRAB, BLRABZ Key A, register modifier 1001 11111 000011 BLRAA, BLRAAZ, BLRAB, BLRABZ Key B, register modifier 101x 11111 0000xx UNALLOCATED 11xx 11111 0000xx UNALLOCATED Loads and Stores 0 0 1 1 0 0 1 1 0 0 Decode fields Instruction page Encoding S A R o3 opc 1xx UNALLOCATED 0 0 0x0 UNALLOCATED 0 0 0 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL LDCLRP 0 0 0 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL LDSETP 0 0 0 1 000 SWPP, SWPPA, SWPPAL, SWPPL SWPP 0 0 0 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL RCWCLRP 0 0 0 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL RCWSWPP 0 0 0 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL RCWSETP 0 0 1 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL LDCLRPL 0 0 1 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL LDSETPL 0 0 1 1 000 SWPP, SWPPA, SWPPAL, SWPPL SWPPL 0 0 1 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL RCWCLRPL 0 0 1 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL RCWSWPPL 0 0 1 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL RCWSETPL 0 1 0 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL LDCLRPA 0 1 0 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL LDSETPA 0 1 0 1 000 SWPP, SWPPA, SWPPAL, SWPPL SWPPA 0 1 0 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL RCWCLRPA 0 1 0 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL RCWSWPPA 0 1 0 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL RCWSETPA 0 1 1 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL LDCLRPAL 0 1 1 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPL LDSETPAL 0 1 1 1 000 SWPP, SWPPA, SWPPAL, SWPPL SWPPAL 0 1 1 1 001 RCWCLRP, RCWCLRPA, RCWCLRPAL, RCWCLRPL RCWCLRPAL 0 1 1 1 010 RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL RCWSWPPAL 0 1 1 1 011 RCWSETP, RCWSETPA, RCWSETPAL, RCWSETPL RCWSETPAL 1 0 0xx UNALLOCATED 1 1 000 UNALLOCATED 1 0 0 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL RCWSCLRP 1 0 0 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL RCWSSWPP 1 0 0 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL RCWSSETP 1 0 1 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL RCWSCLRPL 1 0 1 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL RCWSSWPPL 1 0 1 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL RCWSSETPL 1 1 0 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL RCWSCLRPA 1 1 0 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL RCWSSWPPA 1 1 0 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL RCWSSETPA 1 1 1 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPAL, RCWSCLRPL RCWSCLRPAL 1 1 1 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPAL, RCWSSWPPL RCWSSWPPAL 1 1 1 1 011 RCWSSETP, RCWSSETPA, RCWSSETPAL, RCWSSETPL RCWSSETPAL 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding L opcode x0x1 UNALLOCATED 0101 UNALLOCATED 11xx UNALLOCATED 0 0000 ST4 (multiple structures) No offset 0 0010 ST1 (multiple structures) Four registers 0 0100 ST3 (multiple structures) No offset 0 0110 ST1 (multiple structures) Three registers 0 0111 ST1 (multiple structures) One register 0 1000 ST2 (multiple structures) No offset 0 1010 ST1 (multiple structures) Two registers 1 0000 LD4 (multiple structures) No offset 1 0010 LD1 (multiple structures) Four registers 1 0100 LD3 (multiple structures) No offset 1 0110 LD1 (multiple structures) Three registers 1 0111 LD1 (multiple structures) One register 1 1000 LD2 (multiple structures) No offset 1 1010 LD1 (multiple structures) Two registers 0 0 0 1 1 0 0 1 0 Decode fields Instruction page Encoding L Rm opcode x0x1 UNALLOCATED 0101 UNALLOCATED 11xx UNALLOCATED 0 11111 0000 ST4 (multiple structures) Immediate offset 0 11111 0010 ST1 (multiple structures) Four registers, immediate offset 0 11111 0100 ST3 (multiple structures) Immediate offset 0 11111 0110 ST1 (multiple structures) Three registers, immediate offset 0 11111 0111 ST1 (multiple structures) One register, immediate offset 0 11111 1000 ST2 (multiple structures) Immediate offset 0 11111 1010 ST1 (multiple structures) Two registers, immediate offset 0 != 11111 0000 ST4 (multiple structures) Register offset 0 != 11111 0010 ST1 (multiple structures) Four registers, register offset 0 != 11111 0100 ST3 (multiple structures) Register offset 0 != 11111 0110 ST1 (multiple structures) Three registers, register offset 0 != 11111 0111 ST1 (multiple structures) One register, register offset 0 != 11111 1000 ST2 (multiple structures) Register offset 0 != 11111 1010 ST1 (multiple structures) Two registers, register offset 1 11111 0000 LD4 (multiple structures) Immediate offset 1 11111 0010 LD1 (multiple structures) Four registers, immediate offset 1 11111 0100 LD3 (multiple structures) Immediate offset 1 11111 0110 LD1 (multiple structures) Three registers, immediate offset 1 11111 0111 LD1 (multiple structures) One register, immediate offset 1 11111 1000 LD2 (multiple structures) Immediate offset 1 11111 1010 LD1 (multiple structures) Two registers, immediate offset 1 != 11111 0000 LD4 (multiple structures) Register offset 1 != 11111 0010 LD1 (multiple structures) Four registers, register offset 1 != 11111 0100 LD3 (multiple structures) Register offset 1 != 11111 0110 LD1 (multiple structures) Three registers, register offset 1 != 11111 0111 LD1 (multiple structures) One register, register offset 1 != 11111 1000 LD2 (multiple structures) Register offset 1 != 11111 1010 LD1 (multiple structures) Two registers, register offset 0 0 0 1 1 0 1 0 0 0 0 0 Decode fields Instruction page Encoding L R o2 opcode S size 0 01x x1 UNALLOCATED 0 10x 1x UNALLOCATED 0 10x 1 01 UNALLOCATED 0 1 100 != 01 UNALLOCATED 0 1 100 1 01 UNALLOCATED 0 1 != 100 UNALLOCATED 1 1 UNALLOCATED 0 0 11x UNALLOCATED 0 0 0 000 ST1 (single structure) 8-bit 0 0 0 001 ST3 (single structure) 8-bit 0 0 0 010 x0 ST1 (single structure) 16-bit 0 0 0 011 x0 ST3 (single structure) 16-bit 0 0 0 100 00 ST1 (single structure) 32-bit 0 0 0 100 0 01 ST1 (single structure) 64-bit 0 0 0 101 00 ST3 (single structure) 32-bit 0 0 0 101 0 01 ST3 (single structure) 64-bit 0 0 1 100 0 01 STL1 (SIMD&FP) 0 1 0 000 ST2 (single structure) 8-bit 0 1 0 001 ST4 (single structure) 8-bit 0 1 0 010 x0 ST2 (single structure) 16-bit 0 1 0 011 x0 ST4 (single structure) 16-bit 0 1 0 100 00 ST2 (single structure) 32-bit 0 1 0 100 0 01 ST2 (single structure) 64-bit 0 1 0 101 00 ST4 (single structure) 32-bit 0 1 0 101 0 01 ST4 (single structure) 64-bit 1 0 11x 1 UNALLOCATED 1 0 0 000 LD1 (single structure) 8-bit 1 0 0 001 LD3 (single structure) 8-bit 1 0 0 010 x0 LD1 (single structure) 16-bit 1 0 0 011 x0 LD3 (single structure) 16-bit 1 0 0 100 00 LD1 (single structure) 32-bit 1 0 0 100 0 01 LD1 (single structure) 64-bit 1 0 0 101 00 LD3 (single structure) 32-bit 1 0 0 101 0 01 LD3 (single structure) 64-bit 1 0 0 110 0 LD1R No offset 1 0 0 111 0 LD3R No offset 1 0 1 100 0 01 LDAP1 (SIMD&FP) 1 1 0 000 LD2 (single structure) 8-bit 1 1 0 001 LD4 (single structure) 8-bit 1 1 0 010 x0 LD2 (single structure) 16-bit 1 1 0 011 x0 LD4 (single structure) 16-bit 1 1 0 100 00 LD2 (single structure) 32-bit 1 1 0 100 0 01 LD2 (single structure) 64-bit 1 1 0 101 00 LD4 (single structure) 32-bit 1 1 0 101 0 01 LD4 (single structure) 64-bit 1 1 0 110 0 LD2R No offset 1 1 0 111 0 LD4R No offset 0 0 0 1 1 0 1 1 Decode fields Instruction page Encoding L R Rm opcode S size 01x x1 UNALLOCATED 10x 1x UNALLOCATED 10x 1 01 UNALLOCATED 0 11x UNALLOCATED 0 0 11111 000 ST1 (single structure) 8-bit, immediate offset 0 0 11111 001 ST3 (single structure) 8-bit, immediate offset 0 0 11111 010 x0 ST1 (single structure) 16-bit, immediate offset 0 0 11111 011 x0 ST3 (single structure) 16-bit, immediate offset 0 0 11111 100 00 ST1 (single structure) 32-bit, immediate offset 0 0 11111 100 0 01 ST1 (single structure) 64-bit, immediate offset 0 0 11111 101 00 ST3 (single structure) 32-bit, immediate offset 0 0 11111 101 0 01 ST3 (single structure) 64-bit, immediate offset 0 0 != 11111 000 ST1 (single structure) 8-bit, register offset 0 0 != 11111 001 ST3 (single structure) 8-bit, register offset 0 0 != 11111 010 x0 ST1 (single structure) 16-bit, register offset 0 0 != 11111 011 x0 ST3 (single structure) 16-bit, register offset 0 0 != 11111 100 00 ST1 (single structure) 32-bit, register offset 0 0 != 11111 100 0 01 ST1 (single structure) 64-bit, register offset 0 0 != 11111 101 00 ST3 (single structure) 32-bit, register offset 0 0 != 11111 101 0 01 ST3 (single structure) 64-bit, register offset 0 1 11111 000 ST2 (single structure) 8-bit, immediate offset 0 1 11111 001 ST4 (single structure) 8-bit, immediate offset 0 1 11111 010 x0 ST2 (single structure) 16-bit, immediate offset 0 1 11111 011 x0 ST4 (single structure) 16-bit, immediate offset 0 1 11111 100 00 ST2 (single structure) 32-bit, immediate offset 0 1 11111 100 0 01 ST2 (single structure) 64-bit, immediate offset 0 1 11111 101 00 ST4 (single structure) 32-bit, immediate offset 0 1 11111 101 0 01 ST4 (single structure) 64-bit, immediate offset 0 1 != 11111 000 ST2 (single structure) 8-bit, register offset 0 1 != 11111 001 ST4 (single structure) 8-bit, register offset 0 1 != 11111 010 x0 ST2 (single structure) 16-bit, register offset 0 1 != 11111 011 x0 ST4 (single structure) 16-bit, register offset 0 1 != 11111 100 00 ST2 (single structure) 32-bit, register offset 0 1 != 11111 100 0 01 ST2 (single structure) 64-bit, register offset 0 1 != 11111 101 00 ST4 (single structure) 32-bit, register offset 0 1 != 11111 101 0 01 ST4 (single structure) 64-bit, register offset 1 11x 1 UNALLOCATED 1 0 11111 000 LD1 (single structure) 8-bit, immediate offset 1 0 11111 001 LD3 (single structure) 8-bit, immediate offset 1 0 11111 010 x0 LD1 (single structure) 16-bit, immediate offset 1 0 11111 011 x0 LD3 (single structure) 16-bit, immediate offset 1 0 11111 100 00 LD1 (single structure) 32-bit, immediate offset 1 0 11111 100 0 01 LD1 (single structure) 64-bit, immediate offset 1 0 11111 101 00 LD3 (single structure) 32-bit, immediate offset 1 0 11111 101 0 01 LD3 (single structure) 64-bit, immediate offset 1 0 11111 110 0 LD1R Immediate offset 1 0 11111 111 0 LD3R Immediate offset 1 0 != 11111 000 LD1 (single structure) 8-bit, register offset 1 0 != 11111 001 LD3 (single structure) 8-bit, register offset 1 0 != 11111 010 x0 LD1 (single structure) 16-bit, register offset 1 0 != 11111 011 x0 LD3 (single structure) 16-bit, register offset 1 0 != 11111 100 00 LD1 (single structure) 32-bit, register offset 1 0 != 11111 100 0 01 LD1 (single structure) 64-bit, register offset 1 0 != 11111 101 00 LD3 (single structure) 32-bit, register offset 1 0 != 11111 101 0 01 LD3 (single structure) 64-bit, register offset 1 0 != 11111 110 0 LD1R Register offset 1 0 != 11111 111 0 LD3R Register offset 1 1 11111 000 LD2 (single structure) 8-bit, immediate offset 1 1 11111 001 LD4 (single structure) 8-bit, immediate offset 1 1 11111 010 x0 LD2 (single structure) 16-bit, immediate offset 1 1 11111 011 x0 LD4 (single structure) 16-bit, immediate offset 1 1 11111 100 00 LD2 (single structure) 32-bit, immediate offset 1 1 11111 100 0 01 LD2 (single structure) 64-bit, immediate offset 1 1 11111 101 00 LD4 (single structure) 32-bit, immediate offset 1 1 11111 101 0 01 LD4 (single structure) 64-bit, immediate offset 1 1 11111 110 0 LD2R Immediate offset 1 1 11111 111 0 LD4R Immediate offset 1 1 != 11111 000 LD2 (single structure) 8-bit, register offset 1 1 != 11111 001 LD4 (single structure) 8-bit, register offset 1 1 != 11111 010 x0 LD2 (single structure) 16-bit, register offset 1 1 != 11111 011 x0 LD4 (single structure) 16-bit, register offset 1 1 != 11111 100 00 LD2 (single structure) 32-bit, register offset 1 1 != 11111 100 0 01 LD2 (single structure) 64-bit, register offset 1 1 != 11111 101 00 LD4 (single structure) 32-bit, register offset 1 1 != 11111 101 0 01 LD4 (single structure) 64-bit, register offset 1 1 != 11111 110 0 LD2R Register offset 1 1 != 11111 111 0 LD4R Register offset 1 1 1 0 0 1 0 0 Decode fields Instruction page Encoding size VR A R Rs o3 opc Rt 0 0 1 100 UNALLOCATED 0 0 1 11x UNALLOCATED 0 1 1 1 100 UNALLOCATED 1 0 001 UNALLOCATED 1 0 01x UNALLOCATED 1 0 1 != 11111 UNALLOCATED 1 0 1 001 11111 UNALLOCATED 1 0 1 01x 11111 UNALLOCATED 1 1 1 UNALLOCATED 0x 0 0 1 101 UNALLOCATED 0x 0 0 1 1 101 UNALLOCATED 0x 0 1 1 11x UNALLOCATED 0x 0 1 1 1 101 UNALLOCATED 00 0 0 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB No memory ordering 00 0 0 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB No memory ordering 00 0 0 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB No memory ordering 00 0 0 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB No memory ordering 00 0 0 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB No memory ordering 00 0 0 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB No memory ordering 00 0 0 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB No memory ordering 00 0 0 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB No memory ordering 00 0 0 0 1 000 SWPB, SWPAB, SWPALB, SWPLB SWPB 00 0 0 0 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL RCWCLR 00 0 0 0 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL RCWSWP 00 0 0 0 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL RCWSET 00 0 0 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB Release 00 0 0 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB Release 00 0 0 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB Release 00 0 0 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB Release 00 0 0 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB Release 00 0 0 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB Release 00 0 0 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB Release 00 0 0 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB Release 00 0 0 1 1 000 SWPB, SWPAB, SWPALB, SWPLB SWPLB 00 0 0 1 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL RCWCLRL 00 0 0 1 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL RCWSWPL 00 0 0 1 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL RCWSETL 00 0 1 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB Acquire 00 0 1 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB Acquire 00 0 1 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB Acquire 00 0 1 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB Acquire 00 0 1 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB Acquire 00 0 1 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB Acquire 00 0 1 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB Acquire 00 0 1 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB Acquire 00 0 1 0 1 000 SWPB, SWPAB, SWPALB, SWPLB SWPAB 00 0 1 0 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL RCWCLRA 00 0 1 0 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL RCWSWPA 00 0 1 0 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL RCWSETA 00 0 1 0 1 100 LDAPRB 00 0 1 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLB Acquire-release 00 0 1 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB Acquire-release 00 0 1 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLB Acquire-release 00 0 1 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLB Acquire-release 00 0 1 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB Acquire-release 00 0 1 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB Acquire-release 00 0 1 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB Acquire-release 00 0 1 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB Acquire-release 00 0 1 1 1 000 SWPB, SWPAB, SWPALB, SWPLB SWPALB 00 0 1 1 1 001 RCWCLR, RCWCLRA, RCWCLRAL, RCWCLRL RCWCLRAL 00 0 1 1 1 010 RCWSWP, RCWSWPA, RCWSWPAL, RCWSWPL RCWSWPAL 00 0 1 1 1 011 RCWSET, RCWSETA, RCWSETAL, RCWSETL RCWSETAL 00 1 0 0 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL No memory ordering 00 1 0 0 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL No memory ordering 00 1 0 0 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL No memory ordering 00 1 0 0 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML No memory ordering 00 1 0 0 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML No memory ordering 00 1 0 0 1 000 11111 STBFADD, STBFADDL No memory ordering 00 1 0 0 1 100 11111 STBFMAX, STBFMAXL No memory ordering 00 1 0 0 1 101 11111 STBFMIN, STBFMINL No memory ordering 00 1 0 0 1 110 11111 STBFMAXNM, STBFMAXNML No memory ordering 00 1 0 0 1 111 11111 STBFMINNM, STBFMINNML No memory ordering 00 1 0 1 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL Release 00 1 0 1 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL Release 00 1 0 1 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL Release 00 1 0 1 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML Release 00 1 0 1 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML Release 00 1 0 1 1 000 11111 STBFADD, STBFADDL Release 00 1 0 1 1 100 11111 STBFMAX, STBFMAXL Release 00 1 0 1 1 101 11111 STBFMIN, STBFMINL Release 00 1 0 1 1 110 11111 STBFMAXNM, STBFMAXNML Release 00 1 0 1 1 111 11111 STBFMINNM, STBFMINNML Release 00 1 1 0 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL Acquire 00 1 1 0 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL Acquire 00 1 1 0 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL Acquire 00 1 1 0 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML Acquire 00 1 1 0 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML Acquire 00 1 1 1 0 000 LDBFADD, LDBFADDA, LDBFADDAL, LDBFADDL Acquire-release 00 1 1 1 0 100 LDBFMAX, LDBFMAXA, LDBFMAXAL, LDBFMAXL Acquire-release 00 1 1 1 0 101 LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL Acquire-release 00 1 1 1 0 110 LDBFMAXNM, LDBFMAXNMA, LDBFMAXNMAL, LDBFMAXNML Acquire-release 00 1 1 1 0 111 LDBFMINNM, LDBFMINNMA, LDBFMINNMAL, LDBFMINNML Acquire-release 01 0 0 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH No memory ordering 01 0 0 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH No memory ordering 01 0 0 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH No memory ordering 01 0 0 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH No memory ordering 01 0 0 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH No memory ordering 01 0 0 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH No memory ordering 01 0 0 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH No memory ordering 01 0 0 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH No memory ordering 01 0 0 0 1 000 SWPH, SWPAH, SWPALH, SWPLH SWPH 01 0 0 0 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL RCWSCLR 01 0 0 0 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL RCWSSWP 01 0 0 0 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL RCWSSET 01 0 0 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH Release 01 0 0 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH Release 01 0 0 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH Release 01 0 0 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH Release 01 0 0 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH Release 01 0 0 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH Release 01 0 0 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH Release 01 0 0 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH Release 01 0 0 1 1 000 SWPH, SWPAH, SWPALH, SWPLH SWPLH 01 0 0 1 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL RCWSCLRL 01 0 0 1 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL RCWSSWPL 01 0 0 1 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL RCWSSETL 01 0 1 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH Acquire 01 0 1 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH Acquire 01 0 1 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH Acquire 01 0 1 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH Acquire 01 0 1 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH Acquire 01 0 1 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH Acquire 01 0 1 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH Acquire 01 0 1 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH Acquire 01 0 1 0 1 000 SWPH, SWPAH, SWPALH, SWPLH SWPAH 01 0 1 0 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL RCWSCLRA 01 0 1 0 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL RCWSSWPA 01 0 1 0 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL RCWSSETA 01 0 1 0 1 100 LDAPRH 01 0 1 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLH Acquire-release 01 0 1 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH Acquire-release 01 0 1 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLH Acquire-release 01 0 1 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLH Acquire-release 01 0 1 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH Acquire-release 01 0 1 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH Acquire-release 01 0 1 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH Acquire-release 01 0 1 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH Acquire-release 01 0 1 1 1 000 SWPH, SWPAH, SWPALH, SWPLH SWPALH 01 0 1 1 1 001 RCWSCLR, RCWSCLRA, RCWSCLRAL, RCWSCLRL RCWSCLRAL 01 0 1 1 1 010 RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL RCWSSWPAL 01 0 1 1 1 011 RCWSSET, RCWSSETA, RCWSSETAL, RCWSSETL RCWSSETAL 01 1 0 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Half-precision no memory ordering 01 1 0 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Half-precision no memory ordering 01 1 0 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Half-precision no memory ordering 01 1 0 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Half-precision no memory ordering 01 1 0 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Half-precision no memory ordering 01 1 0 0 1 000 11111 STFADD, STFADDL Half-precision no memory ordering 01 1 0 0 1 100 11111 STFMAX, STFMAXL Half-precision no memory ordering 01 1 0 0 1 101 11111 STFMIN, STFMINL Half-precision no memory ordering 01 1 0 0 1 110 11111 STFMAXNM, STFMAXNML Half-precision no memory ordering 01 1 0 0 1 111 11111 STFMINNM, STFMINNML Half-precision no memory ordering 01 1 0 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Half-precision release 01 1 0 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Half-precision release 01 1 0 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Half-precision release 01 1 0 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Half-precision release 01 1 0 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Half-precision release 01 1 0 1 1 000 11111 STFADD, STFADDL Half-precision release 01 1 0 1 1 100 11111 STFMAX, STFMAXL Half-precision release 01 1 0 1 1 101 11111 STFMIN, STFMINL Half-precision release 01 1 0 1 1 110 11111 STFMAXNM, STFMAXNML Half-precision release 01 1 0 1 1 111 11111 STFMINNM, STFMINNML Half-precision release 01 1 1 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Half-precision acquire 01 1 1 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Half-precision acquire 01 1 1 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Half-precision acquire 01 1 1 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Half-precision acquire 01 1 1 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Half-precision acquire 01 1 1 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Half-precision acquire-release 01 1 1 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Half-precision acquire-release 01 1 1 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Half-precision acquire-release 01 1 1 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Half-precision acquire-release 01 1 1 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Half-precision acquire-release 1x 0 1 1 x01 UNALLOCATED 1x 0 1 1 x1x UNALLOCATED 10 0 0 1 x01 UNALLOCATED 10 0 0 1 010 UNALLOCATED 10 0 0 1 011 UNALLOCATED 10 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL 32-bit no memory ordering 10 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 32-bit no memory ordering 10 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 32-bit no memory ordering 10 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL 32-bit no memory ordering 10 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 32-bit no memory ordering 10 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 32-bit no memory ordering 10 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 32-bit no memory ordering 10 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 32-bit no memory ordering 10 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL 32-bit SWP 10 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL 32-bit release 10 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 32-bit release 10 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 32-bit release 10 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL 32-bit release 10 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 32-bit release 10 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 32-bit release 10 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 32-bit release 10 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 32-bit release 10 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL 32-bit SWPL 10 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL 32-bit acquire 10 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 32-bit acquire 10 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 32-bit acquire 10 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL 32-bit acquire 10 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 32-bit acquire 10 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 32-bit acquire 10 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 32-bit acquire 10 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 32-bit acquire 10 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL 32-bit SWPA 10 0 1 0 1 100 LDAPR 32-bit 10 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL 32-bit acquire-release 10 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 32-bit acquire-release 10 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 32-bit acquire-release 10 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL 32-bit acquire-release 10 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 32-bit acquire-release 10 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 32-bit acquire-release 10 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 32-bit acquire-release 10 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 32-bit acquire-release 10 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL 32-bit SWPAL 10 1 0 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Single-precision no memory ordering 10 1 0 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Single-precision no memory ordering 10 1 0 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Single-precision no memory ordering 10 1 0 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Single-precision no memory ordering 10 1 0 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Single-precision no memory ordering 10 1 0 0 1 000 11111 STFADD, STFADDL Single-precision no memory ordering 10 1 0 0 1 100 11111 STFMAX, STFMAXL Single-precision no memory ordering 10 1 0 0 1 101 11111 STFMIN, STFMINL Single-precision no memory ordering 10 1 0 0 1 110 11111 STFMAXNM, STFMAXNML Single-precision no memory ordering 10 1 0 0 1 111 11111 STFMINNM, STFMINNML Single-precision no memory ordering 10 1 0 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Single-precision release 10 1 0 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Single-precision release 10 1 0 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Single-precision release 10 1 0 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Single-precision release 10 1 0 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Single-precision release 10 1 0 1 1 000 11111 STFADD, STFADDL Single-precision release 10 1 0 1 1 100 11111 STFMAX, STFMAXL Single-precision release 10 1 0 1 1 101 11111 STFMIN, STFMINL Single-precision release 10 1 0 1 1 110 11111 STFMAXNM, STFMAXNML Single-precision release 10 1 0 1 1 111 11111 STFMINNM, STFMINNML Single-precision release 10 1 1 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Single-precision acquire 10 1 1 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Single-precision acquire 10 1 1 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Single-precision acquire 10 1 1 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Single-precision acquire 10 1 1 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Single-precision acquire 10 1 1 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Single-precision acquire-release 10 1 1 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Single-precision acquire-release 10 1 1 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Single-precision acquire-release 10 1 1 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Single-precision acquire-release 10 1 1 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Single-precision acquire-release 11 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL 64-bit no memory ordering 11 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 64-bit no memory ordering 11 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 64-bit no memory ordering 11 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL 64-bit no memory ordering 11 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 64-bit no memory ordering 11 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 64-bit no memory ordering 11 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 64-bit no memory ordering 11 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 64-bit no memory ordering 11 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL 64-bit SWP 11 0 0 0 1 010 ST64BV0 11 0 0 0 1 011 ST64BV 11 0 0 0 11111 1 001 ST64B 11 0 0 0 11111 1 101 LD64B 11 0 0 0 != 11111 1 x01 UNALLOCATED 11 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL 64-bit release 11 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 64-bit release 11 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 64-bit release 11 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL 64-bit release 11 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 64-bit release 11 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 64-bit release 11 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 64-bit release 11 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 64-bit release 11 0 0 1 1 x01 UNALLOCATED 11 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL 64-bit SWPL 11 0 0 1 1 010 UNALLOCATED 11 0 0 1 1 011 UNALLOCATED 11 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL 64-bit acquire 11 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 64-bit acquire 11 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 64-bit acquire 11 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL 64-bit acquire 11 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 64-bit acquire 11 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 64-bit acquire 11 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 64-bit acquire 11 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 64-bit acquire 11 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL 64-bit SWPA 11 0 1 0 1 100 LDAPR 64-bit 11 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL 64-bit acquire-release 11 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL 64-bit acquire-release 11 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL 64-bit acquire-release 11 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL 64-bit acquire-release 11 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL 64-bit acquire-release 11 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL 64-bit acquire-release 11 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL 64-bit acquire-release 11 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL 64-bit acquire-release 11 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL 64-bit SWPAL 11 1 0 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Double-precision no memory ordering 11 1 0 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Double-precision no memory ordering 11 1 0 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Double-precision no memory ordering 11 1 0 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Double-precision no memory ordering 11 1 0 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Double-precision no memory ordering 11 1 0 0 1 000 11111 STFADD, STFADDL Double-precision no memory ordering 11 1 0 0 1 100 11111 STFMAX, STFMAXL Double-precision no memory ordering 11 1 0 0 1 101 11111 STFMIN, STFMINL Double-precision no memory ordering 11 1 0 0 1 110 11111 STFMAXNM, STFMAXNML Double-precision no memory ordering 11 1 0 0 1 111 11111 STFMINNM, STFMINNML Double-precision no memory ordering 11 1 0 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Double-precision release 11 1 0 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Double-precision release 11 1 0 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Double-precision release 11 1 0 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Double-precision release 11 1 0 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Double-precision release 11 1 0 1 1 000 11111 STFADD, STFADDL Double-precision release 11 1 0 1 1 100 11111 STFMAX, STFMAXL Double-precision release 11 1 0 1 1 101 11111 STFMIN, STFMINL Double-precision release 11 1 0 1 1 110 11111 STFMAXNM, STFMAXNML Double-precision release 11 1 0 1 1 111 11111 STFMINNM, STFMINNML Double-precision release 11 1 1 0 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Double-precision acquire 11 1 1 0 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Double-precision acquire 11 1 1 0 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Double-precision acquire 11 1 1 0 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Double-precision acquire 11 1 1 0 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Double-precision acquire 11 1 1 1 0 000 LDFADD, LDFADDA, LDFADDAL, LDFADDL Double-precision acquire-release 11 1 1 1 0 100 LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL Double-precision acquire-release 11 1 1 1 0 101 LDFMIN, LDFMINA, LDFMINAL, LDFMINL Double-precision acquire-release 11 1 1 1 0 110 LDFMAXNM, LDFMAXNMA, LDFMAXNMAL, LDFMAXNML Double-precision acquire-release 11 1 1 1 0 111 LDFMINNM, LDFMINNMA, LDFMINNMAL, LDFMINNML Double-precision acquire-release 0 0 1 1 0 0 1 1 0 1 Decode fields Instruction page Encoding sz A R o3 opc 010 UNALLOCATED 1xx UNALLOCATED 1 0x1 UNALLOCATED 0 0 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 32-bit no memory ordering 0 0 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 32-bit no memory ordering 0 0 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 32-bit no memory ordering 0 0 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL 32-bit SWPT 0 0 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 32-bit release 0 0 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 32-bit release 0 0 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 32-bit release 0 0 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL 32-bit SWPTL 0 1 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 32-bit acquire 0 1 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 32-bit acquire 0 1 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 32-bit acquire 0 1 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL 32-bit SWPTA 0 1 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 32-bit acquire-release 0 1 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 32-bit acquire-release 0 1 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 32-bit acquire-release 0 1 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL 32-bit SWPTAL 1 0 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 64-bit no memory ordering 1 0 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 64-bit no memory ordering 1 0 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 64-bit no memory ordering 1 0 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL 64-bit SWPT 1 0 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 64-bit release 1 0 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 64-bit release 1 0 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 64-bit release 1 0 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL 64-bit SWPTL 1 1 0 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 64-bit acquire 1 1 0 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 64-bit acquire 1 1 0 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 64-bit acquire 1 1 0 1 000 SWPT, SWPTA, SWPTAL, SWPTL 64-bit SWPTA 1 1 1 0 000 LDTADD, LDTADDA, LDTADDAL, LDTADDL 64-bit acquire-release 1 1 1 0 001 LDTCLR, LDTCLRA, LDTCLRAL, LDTCLRL 64-bit acquire-release 1 1 1 0 011 LDTSET, LDTSETA, LDTSETAL, LDTSETL 64-bit acquire-release 1 1 1 1 000 SWPT, SWPTA, SWPTAL, SWPTL 64-bit SWPTAL 0 0 1 0 0 0 1 1 Decode fields Instruction page Encoding size L o0 Rt2 != 11111 UNALLOCATED 00 0 0 11111 CASB, CASAB, CASALB, CASLB CASB 00 0 1 11111 CASB, CASAB, CASALB, CASLB CASLB 00 1 0 11111 CASB, CASAB, CASALB, CASLB CASAB 00 1 1 11111 CASB, CASAB, CASALB, CASLB CASALB 01 0 0 11111 CASH, CASAH, CASALH, CASLH CASH 01 0 1 11111 CASH, CASAH, CASALH, CASLH CASLH 01 1 0 11111 CASH, CASAH, CASALH, CASLH CASAH 01 1 1 11111 CASH, CASAH, CASALH, CASLH CASALH 10 0 0 11111 CAS, CASA, CASAL, CASL 32-bit CAS 10 0 1 11111 CAS, CASA, CASAL, CASL 32-bit CASL 10 1 0 11111 CAS, CASA, CASAL, CASL 32-bit CASA 10 1 1 11111 CAS, CASA, CASAL, CASL 32-bit CASAL 11 0 0 11111 CAS, CASA, CASAL, CASL 64-bit CAS 11 0 1 11111 CAS, CASA, CASAL, CASL 64-bit CASL 11 1 0 11111 CAS, CASA, CASAL, CASL 64-bit CASA 11 1 1 11111 CAS, CASA, CASAL, CASL 64-bit CASAL 1 0 0 1 0 0 1 1 0 Decode fields Instruction page Encoding sz L o0 Rt2 0 UNALLOCATED 1 != 11111 UNALLOCATED 1 0 0 11111 CAST, CASAT, CASALT, CASLT CAST 1 0 1 11111 CAST, CASAT, CASALT, CASLT CASLT 1 1 0 11111 CAST, CASAT, CASALT, CASLT CASAT 1 1 1 11111 CAST, CASAT, CASALT, CASLT CASALT 0 0 0 1 0 0 0 0 1 Decode fields Instruction page Encoding sz L o0 Rt2 != 11111 UNALLOCATED 0 0 0 11111 CASP, CASPA, CASPAL, CASPL 32-bit CASP 0 0 1 11111 CASP, CASPA, CASPAL, CASPL 32-bit CASPL 0 1 0 11111 CASP, CASPA, CASPAL, CASPL 32-bit CASPA 0 1 1 11111 CASP, CASPA, CASPAL, CASPL 32-bit CASPAL 1 0 0 11111 CASP, CASPA, CASPAL, CASPL 64-bit CASP 1 0 1 11111 CASP, CASPA, CASPAL, CASPL 64-bit CASPL 1 1 0 11111 CASP, CASPA, CASPAL, CASPL 64-bit CASPA 1 1 1 11111 CASP, CASPA, CASPAL, CASPL 64-bit CASPAL 0 0 0 1 0 0 1 1 0 Decode fields Instruction page Encoding sz L o0 Rt2 0 UNALLOCATED 1 != 11111 UNALLOCATED 1 0 0 11111 CASPT, CASPAT, CASPALT, CASPLT CASPT 1 0 1 11111 CASPT, CASPAT, CASPALT, CASPLT CASPLT 1 1 0 11111 CASPT, CASPAT, CASPALT, CASPLT CASPAT 1 1 1 11111 CASPT, CASPAT, CASPALT, CASPLT CASPALT 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 1 1 Decode fields Instruction page Encoding opc 000 GCSSTR 001 GCSSTTR 01x UNALLOCATED 1xx UNALLOCATED 0 1 1 0 0 Decode fields Instruction page Encoding opc VR 00 0 LDR (literal) 32-bit 00 1 LDR (literal, SIMD&FP) 32-bit 01 0 LDR (literal) 64-bit 01 1 LDR (literal, SIMD&FP) 64-bit 10 0 LDRSW (literal) 10 1 LDR (literal, SIMD&FP) 128-bit 11 0 PRFM (literal) 11 1 UNALLOCATED 1 0 0 1 0 0 0 0 1 Decode fields Instruction page Encoding sz L o0 0 0 0 STXP 32-bit 0 0 1 STLXP 32-bit 0 1 0 LDXP 32-bit 0 1 1 LDAXP 32-bit 1 0 0 STXP 64-bit 1 0 1 STLXP 64-bit 1 1 0 LDXP 64-bit 1 1 1 LDAXP 64-bit 0 0 1 0 0 0 0 0 Decode fields Instruction page Encoding size L o0 00 0 0 STXRB 00 0 1 STLXRB 00 1 0 LDXRB 00 1 1 LDAXRB 01 0 0 STXRH 01 0 1 STLXRH 01 1 0 LDXRH 01 1 1 LDAXRH 10 0 0 STXR 32-bit 10 0 1 STLXR 32-bit 10 1 0 LDXR 32-bit 10 1 1 LDAXR 32-bit 11 0 0 STXR 64-bit 11 0 1 STLXR 64-bit 11 1 0 LDXR 64-bit 11 1 1 LDAXR 64-bit 1 0 0 1 0 0 1 0 0 Decode fields Instruction page Encoding sz L o0 0 0 0 STTXR 32-bit 0 0 1 STLTXR 32-bit 0 1 0 LDTXR 32-bit 0 1 1 LDATXR 32-bit 1 0 0 STTXR 64-bit 1 0 1 STLTXR 64-bit 1 1 0 LDTXR 64-bit 1 1 1 LDATXR 64-bit 1 1 0 1 1 0 0 1 1 Decode fields Instruction page Encoding opc imm9 op2 00 01 STG Post-index 00 10 STG Signed offset 00 11 STG Pre-index 00 000000000 00 STZGM 01 00 LDG 01 01 STZG Post-index 01 10 STZG Signed offset 01 11 STZG Pre-index 10 01 ST2G Post-index 10 10 ST2G Signed offset 10 11 ST2G Pre-index 10 000000000 00 STGM 11 01 STZ2G Post-index 11 10 STZ2G Signed offset 11 11 STZ2G Pre-index 11 000000000 00 LDGM != 01 != 000000000 00 UNALLOCATED 1 0 1 0 0 0 Decode fields Instruction page Encoding opc VR L 00 0 0 STNP 32-bit 00 0 1 LDNP 32-bit 00 1 0 STNP (SIMD&FP) 32-bit 00 1 1 LDNP (SIMD&FP) 32-bit 01 0 UNALLOCATED 01 1 0 STNP (SIMD&FP) 64-bit 01 1 1 LDNP (SIMD&FP) 64-bit 10 0 0 STNP 64-bit 10 0 1 LDNP 64-bit 10 1 0 STNP (SIMD&FP) 128-bit 10 1 1 LDNP (SIMD&FP) 128-bit 11 0 0 STTNP 11 0 1 LDTNP 11 1 0 STTNP (SIMD&FP) 11 1 1 LDTNP (SIMD&FP) 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding size L o0 00 0 0 STLLRB 00 0 1 STLRB 00 1 0 LDLARB 00 1 1 LDARB 01 0 0 STLLRH 01 0 1 STLRH 01 1 0 LDLARH 01 1 1 LDARH 10 0 0 STLLR 32-bit 10 0 1 STLR 32-bit 10 1 0 LDLAR 32-bit 10 1 1 LDAR 32-bit 11 0 0 STLLR 64-bit 11 0 1 STLR 64-bit 11 1 0 LDLAR 64-bit 11 1 1 LDAR 64-bit 0 1 1 1 0 1 0 1 0 Decode fields Instruction page Encoding size opc 00 00 STLUR (SIMD&FP) 8-bit 00 01 LDAPUR (SIMD&FP) 8-bit 00 10 STLUR (SIMD&FP) 128-bit 00 11 LDAPUR (SIMD&FP) 128-bit 01 00 STLUR (SIMD&FP) 16-bit 01 01 LDAPUR (SIMD&FP) 16-bit 10 00 STLUR (SIMD&FP) 32-bit 10 01 LDAPUR (SIMD&FP) 32-bit 11 00 STLUR (SIMD&FP) 64-bit 11 01 LDAPUR (SIMD&FP) 64-bit != 00 1x UNALLOCATED 0 1 1 0 0 1 0 0 0 Decode fields Instruction page Encoding size opc 00 00 STLURB 00 01 LDAPURB 00 10 LDAPURSB 64-bit 00 11 LDAPURSB 32-bit 01 00 STLURH 01 01 LDAPURH 01 10 LDAPURSH 64-bit 01 11 LDAPURSH 32-bit 10 00 STLUR 32-bit 10 01 LDAPUR 32-bit 10 10 LDAPURSW 10 11 UNALLOCATED 11 00 STLUR 64-bit 11 01 LDAPUR 64-bit 11 1x UNALLOCATED 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Decode fields Instruction page Encoding size L 0x UNALLOCATED 10 0 STLR 32-bit 10 1 LDAPR 32-bit 11 0 STLR 64-bit 11 1 LDAPR 64-bit 0 1 1 0 0 1 0 0 1 0 Decode fields Instruction page Encoding size L opc2 0x UNALLOCATED 1x 001x UNALLOCATED 1x 01xx UNALLOCATED 1x 1xxx UNALLOCATED 10 0 0000 STILP 32-bit pre-index 10 0 0001 STILP 32-bit 10 1 0000 LDIAPP 32-bit post-index 10 1 0001 LDIAPP 32-bit 11 0 0000 STILP 64-bit pre-index 11 0 0001 STILP 64-bit 11 1 0000 LDIAPP 64-bit post-index 11 1 0001 LDIAPP 64-bit 1 1 1 0 0 0 0 1 Decode fields Instruction page Encoding size VR opc 00 0 00 STRB (immediate) Post-index 00 0 01 LDRB (immediate) Post-index 00 0 10 LDRSB (immediate) 64-bit 00 0 11 LDRSB (immediate) 32-bit 00 1 00 STR (immediate, SIMD&FP) 8-bit 00 1 01 LDR (immediate, SIMD&FP) 8-bit 00 1 10 STR (immediate, SIMD&FP) 128-bit 00 1 11 LDR (immediate, SIMD&FP) 128-bit 01 0 00 STRH (immediate) Post-index 01 0 01 LDRH (immediate) Post-index 01 0 10 LDRSH (immediate) 64-bit 01 0 11 LDRSH (immediate) 32-bit 01 1 00 STR (immediate, SIMD&FP) 16-bit 01 1 01 LDR (immediate, SIMD&FP) 16-bit 01 1 1x UNALLOCATED 10 0 00 STR (immediate) 32-bit 10 0 01 LDR (immediate) 32-bit 10 0 10 LDRSW (immediate) Post-index 10 0 11 UNALLOCATED 10 1 00 STR (immediate, SIMD&FP) 32-bit 10 1 01 LDR (immediate, SIMD&FP) 32-bit 10 1 1x UNALLOCATED 11 1x UNALLOCATED 11 0 00 STR (immediate) 64-bit 11 0 01 LDR (immediate) 64-bit 11 1 00 STR (immediate, SIMD&FP) 64-bit 11 1 01 LDR (immediate, SIMD&FP) 64-bit 1 1 1 0 0 0 1 1 Decode fields Instruction page Encoding size VR opc 00 0 00 STRB (immediate) Pre-index 00 0 01 LDRB (immediate) Pre-index 00 0 10 LDRSB (immediate) 64-bit 00 0 11 LDRSB (immediate) 32-bit 00 1 00 STR (immediate, SIMD&FP) 8-bit 00 1 01 LDR (immediate, SIMD&FP) 8-bit 00 1 10 STR (immediate, SIMD&FP) 128-bit 00 1 11 LDR (immediate, SIMD&FP) 128-bit 01 0 00 STRH (immediate) Pre-index 01 0 01 LDRH (immediate) Pre-index 01 0 10 LDRSH (immediate) 64-bit 01 0 11 LDRSH (immediate) 32-bit 01 1 00 STR (immediate, SIMD&FP) 16-bit 01 1 01 LDR (immediate, SIMD&FP) 16-bit 01 1 1x UNALLOCATED 10 0 00 STR (immediate) 32-bit 10 0 01 LDR (immediate) 32-bit 10 0 10 LDRSW (immediate) Pre-index 10 0 11 UNALLOCATED 10 1 00 STR (immediate, SIMD&FP) 32-bit 10 1 01 LDR (immediate, SIMD&FP) 32-bit 10 1 1x UNALLOCATED 11 1x UNALLOCATED 11 0 00 STR (immediate) 64-bit 11 0 01 LDR (immediate) 64-bit 11 1 00 STR (immediate, SIMD&FP) 64-bit 11 1 01 LDR (immediate, SIMD&FP) 64-bit 1 1 1 0 0 1 1 Decode fields Instruction page Encoding size VR M W 11 0 0 0 LDRAA, LDRAB Key A, offset 11 0 0 1 LDRAA, LDRAB Key A, pre-indexed 11 0 1 0 LDRAA, LDRAB Key B, offset 11 0 1 1 LDRAA, LDRAB Key B, pre-indexed 11 1 UNALLOCATED != 11 UNALLOCATED 1 1 1 0 0 1 1 0 Decode fields Instruction page Encoding size VR opc option Rt 00 0 00 011 STRB (register) Shifted register 00 0 00 != 011 STRB (register) Extended register 00 0 01 011 LDRB (register) Shifted register 00 0 01 != 011 LDRB (register) Extended register 00 0 10 011 LDRSB (register) 64-bit with shifted register offset 00 0 10 != 011 LDRSB (register) 64-bit with extended register offset 00 0 11 011 LDRSB (register) 32-bit with shifted register offset 00 0 11 != 011 LDRSB (register) 32-bit with extended register offset 00 1 00 011 STR (register, SIMD&FP) 8-bit with shifted register offset 00 1 00 != 011 STR (register, SIMD&FP) 8-bit with extended register offset 00 1 01 011 LDR (register, SIMD&FP) 8-bit with shifted register offset 00 1 01 != 011 LDR (register, SIMD&FP) 8-bit with extended register offset 00 1 10 STR (register, SIMD&FP) 128-bit 00 1 11 LDR (register, SIMD&FP) 128-bit 01 0 00 STRH (register) 01 0 01 LDRH (register) 01 0 10 LDRSH (register) 64-bit 01 0 11 LDRSH (register) 32-bit 01 1 00 STR (register, SIMD&FP) 16-bit 01 1 01 LDR (register, SIMD&FP) 16-bit 1x 0 11 UNALLOCATED 10 0 00 STR (register) 32-bit 10 0 01 LDR (register) 32-bit 10 0 10 LDRSW (register) 10 1 00 STR (register, SIMD&FP) 32-bit 10 1 01 LDR (register, SIMD&FP) 32-bit 11 0 00 STR (register) 64-bit 11 0 01 LDR (register) 64-bit 11 0 10 x0x UNALLOCATED 11 0 10 x1x 11xxx RPRFM 11 0 10 x1x != 11xxx PRFM (register) 11 1 00 STR (register, SIMD&FP) 64-bit 11 1 01 LDR (register, SIMD&FP) 64-bit != 00 1 1x UNALLOCATED 1 1 1 0 0 0 1 0 Decode fields Instruction page Encoding size VR opc 1 UNALLOCATED 00 0 00 STTRB 00 0 01 LDTRB 00 0 10 LDTRSB 64-bit 00 0 11 LDTRSB 32-bit 01 0 00 STTRH 01 0 01 LDTRH 01 0 10 LDTRSH 64-bit 01 0 11 LDTRSH 32-bit 10 0 00 STTR 32-bit 10 0 01 LDTR 32-bit 10 0 10 LDTRSW 10 0 11 UNALLOCATED 11 0 00 STTR 64-bit 11 0 01 LDTR 64-bit 11 0 1x UNALLOCATED 1 1 1 0 0 0 0 0 Decode fields Instruction page Encoding size VR opc 00 0 00 STURB 00 0 01 LDURB 00 0 10 LDURSB 64-bit 00 0 11 LDURSB 32-bit 00 1 00 STUR (SIMD&FP) 8-bit 00 1 01 LDUR (SIMD&FP) 8-bit 00 1 10 STUR (SIMD&FP) 128-bit 00 1 11 LDUR (SIMD&FP) 128-bit 01 0 00 STURH 01 0 01 LDURH 01 0 10 LDURSH 64-bit 01 0 11 LDURSH 32-bit 01 1 00 STUR (SIMD&FP) 16-bit 01 1 01 LDUR (SIMD&FP) 16-bit 1x 0 11 UNALLOCATED 10 0 00 STUR 32-bit 10 0 01 LDUR 32-bit 10 0 10 LDURSW 10 1 00 STUR (SIMD&FP) 32-bit 10 1 01 LDUR (SIMD&FP) 32-bit 11 0 00 STUR 64-bit 11 0 01 LDUR 64-bit 11 0 10 PRFUM 11 1 00 STUR (SIMD&FP) 64-bit 11 1 01 LDUR (SIMD&FP) 64-bit != 00 1 1x UNALLOCATED 1 1 1 0 1 Decode fields Instruction page Encoding size VR opc 00 0 00 STRB (immediate) Unsigned offset 00 0 01 LDRB (immediate) Unsigned offset 00 0 10 LDRSB (immediate) 64-bit 00 0 11 LDRSB (immediate) 32-bit 00 1 00 STR (immediate, SIMD&FP) 8-bit 00 1 01 LDR (immediate, SIMD&FP) 8-bit 00 1 10 STR (immediate, SIMD&FP) 128-bit 00 1 11 LDR (immediate, SIMD&FP) 128-bit 01 0 00 STRH (immediate) Unsigned offset 01 0 01 LDRH (immediate) Unsigned offset 01 0 10 LDRSH (immediate) 64-bit 01 0 11 LDRSH (immediate) 32-bit 01 1 00 STR (immediate, SIMD&FP) 16-bit 01 1 01 LDR (immediate, SIMD&FP) 16-bit 1x 0 11 UNALLOCATED 10 0 00 STR (immediate) 32-bit 10 0 01 LDR (immediate) 32-bit 10 0 10 LDRSW (immediate) Unsigned offset 10 1 00 STR (immediate, SIMD&FP) 32-bit 10 1 01 LDR (immediate, SIMD&FP) 32-bit 11 0 00 STR (immediate) 64-bit 11 0 01 LDR (immediate) 64-bit 11 0 10 PRFM (immediate) 11 1 00 STR (immediate, SIMD&FP) 64-bit 11 1 01 LDR (immediate, SIMD&FP) 64-bit != 00 1 1x UNALLOCATED 1 0 1 0 1 0 Decode fields Instruction page Encoding opc VR L 00 0 0 STP 32-bit 00 0 1 LDP 32-bit 00 1 0 STP (SIMD&FP) 32-bit 00 1 1 LDP (SIMD&FP) 32-bit 01 0 0 STGP Signed offset 01 0 1 LDPSW Signed offset 01 1 0 STP (SIMD&FP) 64-bit 01 1 1 LDP (SIMD&FP) 64-bit 10 0 0 STP 64-bit 10 0 1 LDP 64-bit 10 1 0 STP (SIMD&FP) 128-bit 10 1 1 LDP (SIMD&FP) 128-bit 11 0 0 STTP 11 0 1 LDTP 11 1 0 STTP (SIMD&FP) 11 1 1 LDTP (SIMD&FP) 1 0 1 0 0 1 Decode fields Instruction page Encoding opc VR L 00 0 0 STP 32-bit 00 0 1 LDP 32-bit 00 1 0 STP (SIMD&FP) 32-bit 00 1 1 LDP (SIMD&FP) 32-bit 01 0 0 STGP Post-index 01 0 1 LDPSW Post-index 01 1 0 STP (SIMD&FP) 64-bit 01 1 1 LDP (SIMD&FP) 64-bit 10 0 0 STP 64-bit 10 0 1 LDP 64-bit 10 1 0 STP (SIMD&FP) 128-bit 10 1 1 LDP (SIMD&FP) 128-bit 11 0 0 STTP 11 0 1 LDTP 11 1 0 STTP (SIMD&FP) 11 1 1 LDTP (SIMD&FP) 1 0 1 0 1 1 Decode fields Instruction page Encoding opc VR L 00 0 0 STP 32-bit 00 0 1 LDP 32-bit 00 1 0 STP (SIMD&FP) 32-bit 00 1 1 LDP (SIMD&FP) 32-bit 01 0 0 STGP Pre-index 01 0 1 LDPSW Pre-index 01 1 0 STP (SIMD&FP) 64-bit 01 1 1 LDP (SIMD&FP) 64-bit 10 0 0 STP 64-bit 10 0 1 LDP 64-bit 10 1 0 STP (SIMD&FP) 128-bit 10 1 1 LDP (SIMD&FP) 128-bit 11 0 0 STTP 11 0 1 LDTP 11 1 0 STTP (SIMD&FP) 11 1 1 LDTP (SIMD&FP) 0 1 1 0 1 0 0 1 Decode fields Instruction page Encoding o0 op1 op2 11 11xx UNALLOCATED 0 00 0000 CPYFP, CPYFM, CPYFE Prologue 0 00 0001 CPYFPWT, CPYFMWT, CPYFEWT Prologue 0 00 0010 CPYFPRT, CPYFMRT, CPYFERT Prologue 0 00 0011 CPYFPT, CPYFMT, CPYFET Prologue 0 00 0100 CPYFPWN, CPYFMWN, CPYFEWN Prologue 0 00 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN Prologue 0 00 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWN Prologue 0 00 0111 CPYFPTWN, CPYFMTWN, CPYFETWN Prologue 0 00 1000 CPYFPRN, CPYFMRN, CPYFERN Prologue 0 00 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN Prologue 0 00 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRN Prologue 0 00 1011 CPYFPTRN, CPYFMTRN, CPYFETRN Prologue 0 00 1100 CPYFPN, CPYFMN, CPYFEN Prologue 0 00 1101 CPYFPWTN, CPYFMWTN, CPYFEWTN Prologue 0 00 1110 CPYFPRTN, CPYFMRTN, CPYFERTN Prologue 0 00 1111 CPYFPTN, CPYFMTN, CPYFETN Prologue 0 01 0000 CPYFP, CPYFM, CPYFE Main 0 01 0001 CPYFPWT, CPYFMWT, CPYFEWT Main 0 01 0010 CPYFPRT, CPYFMRT, CPYFERT Main 0 01 0011 CPYFPT, CPYFMT, CPYFET Main 0 01 0100 CPYFPWN, CPYFMWN, CPYFEWN Main 0 01 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN Main 0 01 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWN Main 0 01 0111 CPYFPTWN, CPYFMTWN, CPYFETWN Main 0 01 1000 CPYFPRN, CPYFMRN, CPYFERN Main 0 01 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN Main 0 01 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRN Main 0 01 1011 CPYFPTRN, CPYFMTRN, CPYFETRN Main 0 01 1100 CPYFPN, CPYFMN, CPYFEN Main 0 01 1101 CPYFPWTN, CPYFMWTN, CPYFEWTN Main 0 01 1110 CPYFPRTN, CPYFMRTN, CPYFERTN Main 0 01 1111 CPYFPTN, CPYFMTN, CPYFETN Main 0 10 0000 CPYFP, CPYFM, CPYFE Epilogue 0 10 0001 CPYFPWT, CPYFMWT, CPYFEWT Epilogue 0 10 0010 CPYFPRT, CPYFMRT, CPYFERT Epilogue 0 10 0011 CPYFPT, CPYFMT, CPYFET Epilogue 0 10 0100 CPYFPWN, CPYFMWN, CPYFEWN Epilogue 0 10 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWN Epilogue 0 10 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWN Epilogue 0 10 0111 CPYFPTWN, CPYFMTWN, CPYFETWN Epilogue 0 10 1000 CPYFPRN, CPYFMRN, CPYFERN Epilogue 0 10 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRN Epilogue 0 10 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRN Epilogue 0 10 1011 CPYFPTRN, CPYFMTRN, CPYFETRN Epilogue 0 10 1100 CPYFPN, CPYFMN, CPYFEN Epilogue 0 10 1101 CPYFPWTN, CPYFMWTN, CPYFEWTN Epilogue 0 10 1110 CPYFPRTN, CPYFMRTN, CPYFERTN Epilogue 0 10 1111 CPYFPTN, CPYFMTN, CPYFETN Epilogue 0 11 0000 SETP, SETM, SETE Prologue 0 11 0001 SETPT, SETMT, SETET Prologue 0 11 0010 SETPN, SETMN, SETEN Prologue 0 11 0011 SETPTN, SETMTN, SETETN Prologue 0 11 0100 SETP, SETM, SETE Main 0 11 0101 SETPT, SETMT, SETET Main 0 11 0110 SETPN, SETMN, SETEN Main 0 11 0111 SETPTN, SETMTN, SETETN Main 0 11 1000 SETP, SETM, SETE Epilogue 0 11 1001 SETPT, SETMT, SETET Epilogue 0 11 1010 SETPN, SETMN, SETEN Epilogue 0 11 1011 SETPTN, SETMTN, SETETN Epilogue 1 00 0000 CPYP, CPYM, CPYE Prologue 1 00 0001 CPYPWT, CPYMWT, CPYEWT Prologue 1 00 0010 CPYPRT, CPYMRT, CPYERT Prologue 1 00 0011 CPYPT, CPYMT, CPYET Prologue 1 00 0100 CPYPWN, CPYMWN, CPYEWN Prologue 1 00 0101 CPYPWTWN, CPYMWTWN, CPYEWTWN Prologue 1 00 0110 CPYPRTWN, CPYMRTWN, CPYERTWN Prologue 1 00 0111 CPYPTWN, CPYMTWN, CPYETWN Prologue 1 00 1000 CPYPRN, CPYMRN, CPYERN Prologue 1 00 1001 CPYPWTRN, CPYMWTRN, CPYEWTRN Prologue 1 00 1010 CPYPRTRN, CPYMRTRN, CPYERTRN Prologue 1 00 1011 CPYPTRN, CPYMTRN, CPYETRN Prologue 1 00 1100 CPYPN, CPYMN, CPYEN Prologue 1 00 1101 CPYPWTN, CPYMWTN, CPYEWTN Prologue 1 00 1110 CPYPRTN, CPYMRTN, CPYERTN Prologue 1 00 1111 CPYPTN, CPYMTN, CPYETN Prologue 1 01 0000 CPYP, CPYM, CPYE Main 1 01 0001 CPYPWT, CPYMWT, CPYEWT Main 1 01 0010 CPYPRT, CPYMRT, CPYERT Main 1 01 0011 CPYPT, CPYMT, CPYET Main 1 01 0100 CPYPWN, CPYMWN, CPYEWN Main 1 01 0101 CPYPWTWN, CPYMWTWN, CPYEWTWN Main 1 01 0110 CPYPRTWN, CPYMRTWN, CPYERTWN Main 1 01 0111 CPYPTWN, CPYMTWN, CPYETWN Main 1 01 1000 CPYPRN, CPYMRN, CPYERN Main 1 01 1001 CPYPWTRN, CPYMWTRN, CPYEWTRN Main 1 01 1010 CPYPRTRN, CPYMRTRN, CPYERTRN Main 1 01 1011 CPYPTRN, CPYMTRN, CPYETRN Main 1 01 1100 CPYPN, CPYMN, CPYEN Main 1 01 1101 CPYPWTN, CPYMWTN, CPYEWTN Main 1 01 1110 CPYPRTN, CPYMRTN, CPYERTN Main 1 01 1111 CPYPTN, CPYMTN, CPYETN Main 1 10 0000 CPYP, CPYM, CPYE Epilogue 1 10 0001 CPYPWT, CPYMWT, CPYEWT Epilogue 1 10 0010 CPYPRT, CPYMRT, CPYERT Epilogue 1 10 0011 CPYPT, CPYMT, CPYET Epilogue 1 10 0100 CPYPWN, CPYMWN, CPYEWN Epilogue 1 10 0101 CPYPWTWN, CPYMWTWN, CPYEWTWN Epilogue 1 10 0110 CPYPRTWN, CPYMRTWN, CPYERTWN Epilogue 1 10 0111 CPYPTWN, CPYMTWN, CPYETWN Epilogue 1 10 1000 CPYPRN, CPYMRN, CPYERN Epilogue 1 10 1001 CPYPWTRN, CPYMWTRN, CPYEWTRN Epilogue 1 10 1010 CPYPRTRN, CPYMRTRN, CPYERTRN Epilogue 1 10 1011 CPYPTRN, CPYMTRN, CPYETRN Epilogue 1 10 1100 CPYPN, CPYMN, CPYEN Epilogue 1 10 1101 CPYPWTN, CPYMWTN, CPYEWTN Epilogue 1 10 1110 CPYPRTN, CPYMRTN, CPYERTN Epilogue 1 10 1111 CPYPTN, CPYMTN, CPYETN Epilogue 1 11 0000 SETGP, SETGM, SETGE Prologue 1 11 0001 SETGPT, SETGMT, SETGET Prologue 1 11 0010 SETGPN, SETGMN, SETGEN Prologue 1 11 0011 SETGPTN, SETGMTN, SETGETN Prologue 1 11 0100 SETGP, SETGM, SETGE Main 1 11 0101 SETGPT, SETGMT, SETGET Main 1 11 0110 SETGPN, SETGMN, SETGEN Main 1 11 0111 SETGPTN, SETGMTN, SETGETN Main 1 11 1000 SETGP, SETGM, SETGE Epilogue 1 11 1001 SETGPT, SETGMT, SETGET Epilogue 1 11 1010 SETGPN, SETGMN, SETGEN Epilogue 1 11 1011 SETGPTN, SETGMTN, SETGETN Epilogue 0 0 1 1 0 0 1 1 0 0 0 0 1 0 Decode fields Instruction page Encoding S A R 0 0 0 RCWCAS, RCWCASA, RCWCASAL, RCWCASL RCWCAS 0 0 1 RCWCAS, RCWCASA, RCWCASAL, RCWCASL RCWCASL 0 1 0 RCWCAS, RCWCASA, RCWCASAL, RCWCASL RCWCASA 0 1 1 RCWCAS, RCWCASA, RCWCASAL, RCWCASL RCWCASAL 1 0 0 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL RCWSCAS 1 0 1 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL RCWSCASL 1 1 0 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL RCWSCASA 1 1 1 RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL RCWSCASAL 0 0 1 1 0 0 1 1 0 0 0 0 1 1 Decode fields Instruction page Encoding S A R 0 0 0 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL RCWCASP 0 0 1 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL RCWCASPL 0 1 0 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL RCWCASPA 0 1 1 RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL RCWCASPAL 1 0 0 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL RCWSCASP 1 0 1 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL RCWSCASPL 1 1 0 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL RCWSCASPA 1 1 1 RCWSCASP, RCWSCASPA, RCWSCASPAL, RCWSCASPL RCWSCASPAL Data Processing -- Immediate 1 0 0 0 1 0 Decode fields Instruction page Encoding sf op S 0 0 0 ADD (immediate) 32-bit 0 0 1 ADDS (immediate) 32-bit 0 1 0 SUB (immediate) 32-bit 0 1 1 SUBS (immediate) 32-bit 1 0 0 ADD (immediate) 64-bit 1 0 1 ADDS (immediate) 64-bit 1 1 0 SUB (immediate) 64-bit 1 1 1 SUBS (immediate) 64-bit 1 0 0 0 1 1 0 Decode fields Instruction page Encoding sf op S 0 UNALLOCATED 1 1 UNALLOCATED 1 0 0 ADDG 1 1 0 SUBG 1 0 0 1 1 0 Decode fields Instruction page Encoding sf opc N 0 1 UNALLOCATED 0 00 0 SBFM 32-bit 0 01 0 BFM 32-bit 0 10 0 UBFM 32-bit 0 11 0 UNALLOCATED 1 0 UNALLOCATED 1 00 1 SBFM 64-bit 1 01 1 BFM 64-bit 1 10 1 UBFM 64-bit 1 11 1 UNALLOCATED 1 1 1 0 0 1 1 1 Decode fields Instruction page Encoding sf opc Rd 0 UNALLOCATED 1 0x != 11111 UNALLOCATED 1 00 11111 AUTIASPPC 1 01 11111 AUTIBSPPC 1 1x UNALLOCATED != 11 1 0 0 1 1 1 Decode fields Instruction page Encoding sf op21 N o0 imms 00 1 UNALLOCATED 01 UNALLOCATED 10 UNALLOCATED 0 00 0 0 0xxxxx EXTR 32-bit 0 00 0 0 1xxxxx UNALLOCATED 0 00 1 0 UNALLOCATED 1 00 0 0 UNALLOCATED 1 00 1 0 EXTR 64-bit 1 0 0 1 0 0 Decode fields Instruction page Encoding sf opc N 0 1 UNALLOCATED 0 00 0 AND (immediate) 32-bit 0 01 0 ORR (immediate) 32-bit 0 10 0 EOR (immediate) 32-bit 0 11 0 ANDS (immediate) 32-bit 1 00 AND (immediate) 64-bit 1 01 ORR (immediate) 64-bit 1 10 EOR (immediate) 64-bit 1 11 ANDS (immediate) 64-bit 1 0 0 0 1 1 1 Decode fields Instruction page Encoding sf op S opc 0 0 01xx UNALLOCATED 0 0 1xxx UNALLOCATED 0 1 UNALLOCATED 1 UNALLOCATED 0 0 0 0000 SMAX (immediate) 32-bit 0 0 0 0001 UMAX (immediate) 32-bit 0 0 0 0010 SMIN (immediate) 32-bit 0 0 0 0011 UMIN (immediate) 32-bit 1 0 0 0000 SMAX (immediate) 64-bit 1 0 0 0001 UMAX (immediate) 64-bit 1 0 0 0010 SMIN (immediate) 64-bit 1 0 0 0011 UMIN (immediate) 64-bit 1 0 0 1 0 1 Decode fields Instruction page Encoding sf opc hw 01 0x UNALLOCATED 0 1x UNALLOCATED 0 00 0x MOVN 32-bit 0 10 0x MOVZ 32-bit 0 11 0x MOVK 32-bit 1 00 MOVN 64-bit 1 01 1x UNALLOCATED 1 10 MOVZ 64-bit 1 11 MOVK 64-bit 1 0 0 0 0 Decode fields Instruction page Encoding op 0 ADR 1 ADRP Data Processing -- Register 1 1 0 1 0 0 0 0 0 0 1 Decode fields Instruction page Encoding sf op S 0 UNALLOCATED 1 1 UNALLOCATED 1 0 0 ADDPT 1 1 0 SUBPT 0 1 0 1 1 1 Decode fields Instruction page Encoding sf op S opt != 00 UNALLOCATED 0 0 0 00 ADD (extended register) 32-bit 0 0 1 00 ADDS (extended register) 32-bit 0 1 0 00 SUB (extended register) 32-bit 0 1 1 00 SUBS (extended register) 32-bit 1 0 0 00 ADD (extended register) 64-bit 1 0 1 00 ADDS (extended register) 64-bit 1 1 0 00 SUB (extended register) 64-bit 1 1 1 00 SUBS (extended register) 64-bit 0 1 0 1 1 0 Decode fields Instruction page Encoding sf op S 0 0 0 ADD (shifted register) 32-bit 0 0 1 ADDS (shifted register) 32-bit 0 1 0 SUB (shifted register) 32-bit 0 1 1 SUBS (shifted register) 32-bit 1 0 0 ADD (shifted register) 64-bit 1 0 1 ADDS (shifted register) 64-bit 1 1 0 SUB (shifted register) 64-bit 1 1 1 SUBS (shifted register) 64-bit 1 1 0 1 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding sf op S 0 0 0 ADC 32-bit 0 0 1 ADCS 32-bit 0 1 0 SBC 32-bit 0 1 1 SBCS 32-bit 1 0 0 ADC 64-bit 1 0 1 ADCS 64-bit 1 1 0 SBC 64-bit 1 1 1 SBCS 64-bit 1 1 0 1 0 0 1 0 1 Decode fields Instruction page Encoding sf op S o2 o3 0 UNALLOCATED 1 0 1 UNALLOCATED 1 1 UNALLOCATED 0 0 1 0 0 CCMN (immediate) 32-bit 0 1 1 0 0 CCMP (immediate) 32-bit 1 0 1 0 0 CCMN (immediate) 64-bit 1 1 1 0 0 CCMP (immediate) 64-bit 1 1 0 1 0 0 1 0 0 Decode fields Instruction page Encoding sf op S o2 o3 0 UNALLOCATED 1 0 1 UNALLOCATED 1 1 UNALLOCATED 0 0 1 0 0 CCMN (register) 32-bit 0 1 1 0 0 CCMP (register) 32-bit 1 0 1 0 0 CCMN (register) 64-bit 1 1 1 0 0 CCMP (register) 64-bit 1 1 0 1 0 1 0 0 Decode fields Instruction page Encoding sf op S op2 0 1x UNALLOCATED 1 UNALLOCATED 0 0 0 00 CSEL 32-bit 0 0 0 01 CSINC 32-bit 0 1 0 00 CSINV 32-bit 0 1 0 01 CSNEG 32-bit 1 0 0 00 CSEL 64-bit 1 0 0 01 CSINC 64-bit 1 1 0 00 CSINV 64-bit 1 1 0 01 CSNEG 64-bit 1 1 1 0 1 0 1 1 0 Decode fields Instruction page Encoding sf S opcode2 opcode Rn Rd 0 00000 001001 UNALLOCATED 0 00000 00101x UNALLOCATED 0 00000 0011xx UNALLOCATED 0 00000 01xxxx UNALLOCATED 0 00000 1xxxxx UNALLOCATED 0 0001x UNALLOCATED 0 001xx UNALLOCATED 0 01xxx UNALLOCATED 0 1xxxx UNALLOCATED 1 UNALLOCATED 0 0 00000 000000 RBIT 32-bit 0 0 00000 000001 REV16 32-bit 0 0 00000 000010 REV 32-bit 0 0 00000 000011 UNALLOCATED 0 0 00000 000100 CLZ 32-bit 0 0 00000 000101 CLS 32-bit 0 0 00000 000110 CTZ 32-bit 0 0 00000 000111 CNT 32-bit 0 0 00000 001000 ABS 32-bit 0 0 00001 UNALLOCATED 1 0 00000 000000 RBIT 64-bit 1 0 00000 000001 REV16 64-bit 1 0 00000 000010 REV32 1 0 00000 000011 REV 64-bit 1 0 00000 000100 CLZ 64-bit 1 0 00000 000101 CLS 64-bit 1 0 00000 000110 CTZ 64-bit 1 0 00000 000111 CNT 64-bit 1 0 00000 001000 ABS 64-bit 1 0 00001 000000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA PACIA 1 0 00001 000001 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB PACIB 1 0 00001 000010 PACDA, PACDZA PACDA 1 0 00001 000011 PACDB, PACDZB PACDB 1 0 00001 000100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA AUTIA 1 0 00001 000101 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB AUTIB 1 0 00001 000110 AUTDA, AUTDZA AUTDA 1 0 00001 000111 AUTDB, AUTDZB AUTDB 1 0 00001 001xxx != 11111 UNALLOCATED 1 0 00001 001000 11111 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA PACIZA 1 0 00001 001001 11111 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB PACIZB 1 0 00001 001010 11111 PACDA, PACDZA PACDZA 1 0 00001 001011 11111 PACDB, PACDZB PACDZB 1 0 00001 001100 11111 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA AUTIZA 1 0 00001 001101 11111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB AUTIZB 1 0 00001 001110 11111 AUTDA, AUTDZA AUTDZA 1 0 00001 001111 11111 AUTDB, AUTDZB AUTDZB 1 0 00001 01000x != 11111 UNALLOCATED 1 0 00001 010000 11111 XPACD, XPACI, XPACLRI XPACI 1 0 00001 010001 11111 XPACD, XPACI, XPACLRI XPACD 1 0 00001 01001x UNALLOCATED 1 0 00001 0101xx UNALLOCATED 1 0 00001 011xxx UNALLOCATED 1 0 00001 10xxxx != 11110 UNALLOCATED 1 0 00001 1000xx != 11111 11110 UNALLOCATED 1 0 00001 100000 11111 11110 PACNBIASPPC 1 0 00001 100001 11111 11110 PACNBIBSPPC 1 0 00001 100010 11111 11110 PACIA171615 1 0 00001 100011 11111 11110 PACIB171615 1 0 00001 100100 11110 AUTIASPPCR 1 0 00001 100101 11110 AUTIBSPPCR 1 0 00001 10011x 11110 UNALLOCATED 1 0 00001 101xxx != 11111 11110 UNALLOCATED 1 0 00001 101000 11111 11110 PACIASPPC 1 0 00001 101001 11111 11110 PACIBSPPC 1 0 00001 10101x 11111 11110 UNALLOCATED 1 0 00001 10110x 11111 11110 UNALLOCATED 1 0 00001 101110 11111 11110 AUTIA171615 1 0 00001 101111 11111 11110 AUTIB171615 1 0 00001 11xxxx UNALLOCATED 0 1 1 0 1 0 1 1 0 Decode fields Instruction page Encoding sf S opcode 1xxxxx UNALLOCATED 0 00011x UNALLOCATED 1 00001x UNALLOCATED 1 0001xx UNALLOCATED 1 001xxx UNALLOCATED 1 01xxxx UNALLOCATED 0 00000x UNALLOCATED 0 0 0x11xx UNALLOCATED 0 0 000010 UDIV 32-bit 0 0 000011 SDIV 32-bit 0 0 00010x UNALLOCATED 0 0 001000 LSLV 32-bit 0 0 001001 LSRV 32-bit 0 0 001010 ASRV 32-bit 0 0 001011 RORV 32-bit 0 0 010x11 UNALLOCATED 0 0 010000 CRC32B, CRC32H, CRC32W, CRC32X CRC32B 0 0 010001 CRC32B, CRC32H, CRC32W, CRC32X CRC32H 0 0 010010 CRC32B, CRC32H, CRC32W, CRC32X CRC32W 0 0 010100 CRC32CB, CRC32CH, CRC32CW, CRC32CX CRC32CB 0 0 010101 CRC32CB, CRC32CH, CRC32CW, CRC32CX CRC32CH 0 0 010110 CRC32CB, CRC32CH, CRC32CW, CRC32CX CRC32CW 0 0 011000 SMAX (register) 32-bit 0 0 011001 UMAX (register) 32-bit 0 0 011010 SMIN (register) 32-bit 0 0 011011 UMIN (register) 32-bit 1 000001 UNALLOCATED 1 0 000000 SUBP 1 0 000010 UDIV 64-bit 1 0 000011 SDIV 64-bit 1 0 000100 IRG 1 0 000101 GMI 1 0 001000 LSLV 64-bit 1 0 001001 LSRV 64-bit 1 0 001010 ASRV 64-bit 1 0 001011 RORV 64-bit 1 0 001100 PACGA 1 0 001101 UNALLOCATED 1 0 00111x UNALLOCATED 1 0 010xx0 UNALLOCATED 1 0 010001 UNALLOCATED 1 0 010011 CRC32B, CRC32H, CRC32W, CRC32X CRC32X 1 0 010101 UNALLOCATED 1 0 010111 CRC32CB, CRC32CH, CRC32CW, CRC32CX CRC32CX 1 0 011000 SMAX (register) 64-bit 1 0 011001 UMAX (register) 64-bit 1 0 011010 SMIN (register) 64-bit 1 0 011011 UMIN (register) 64-bit 1 0 0111xx UNALLOCATED 1 1 000000 SUBPS 1 1 0 1 1 Decode fields Instruction page Encoding sf op54 op31 o0 00 100 UNALLOCATED != 00 UNALLOCATED 0 00 x01 UNALLOCATED 0 00 x1x UNALLOCATED 0 00 000 0 MADD 32-bit 0 00 000 1 MSUB 32-bit 1 00 x10 1 UNALLOCATED 1 00 000 0 MADD 64-bit 1 00 000 1 MSUB 64-bit 1 00 001 0 SMADDL 1 00 001 1 SMSUBL 1 00 010 0 SMULH 1 00 011 0 MADDPT 1 00 011 1 MSUBPT 1 00 101 0 UMADDL 1 00 101 1 UMSUBL 1 00 110 0 UMULH 1 00 111 UNALLOCATED 1 1 0 1 0 0 0 0 0 0 1 0 Decode fields Instruction page Encoding sf op S opcode2 sz o3 mask 0 0 0 UNALLOCATED 0 0 1 000000 0 != 1101 UNALLOCATED 0 0 1 000000 1 UNALLOCATED 0 0 1 000000 0 0 1101 SETF8, SETF16 SETF8 0 0 1 000000 1 0 1101 SETF8, SETF16 SETF16 0 0 1 != 000000 UNALLOCATED 0 1 UNALLOCATED 1 UNALLOCATED 0 1 0 1 0 Decode fields Instruction page Encoding sf opc N 0 00 0 AND (shifted register) 32-bit 0 00 1 BIC (shifted register) 32-bit 0 01 0 ORR (shifted register) 32-bit 0 01 1 ORN (shifted register) 32-bit 0 10 0 EOR (shifted register) 32-bit 0 10 1 EON (shifted register) 32-bit 0 11 0 ANDS (shifted register) 32-bit 0 11 1 BICS (shifted register) 32-bit 1 00 0 AND (shifted register) 64-bit 1 00 1 BIC (shifted register) 64-bit 1 01 0 ORR (shifted register) 64-bit 1 01 1 ORN (shifted register) 64-bit 1 10 0 EOR (shifted register) 64-bit 1 10 1 EON (shifted register) 64-bit 1 11 0 ANDS (shifted register) 64-bit 1 11 1 BICS (shifted register) 64-bit 1 1 0 1 0 0 0 0 0 0 0 0 1 Decode fields Instruction page Encoding sf op S o2 0 UNALLOCATED 1 0 0 UNALLOCATED 1 0 1 0 RMIF 1 0 1 1 UNALLOCATED 1 1 UNALLOCATED Data Processing -- Scalar Floating-Point and Advanced SIMD 0 0 1 1 1 0 1 1 0 0 0 1 0 Decode fields Instruction page Encoding Q U size opcode x100x UNALLOCATED 000x0 UNALLOCATED 00001 UNALLOCATED 01011 UNALLOCATED 100xx UNALLOCATED x0 001xx UNALLOCATED x0 01101 UNALLOCATED x0 101xx UNALLOCATED x0 111xx UNALLOCATED x1 xx1xx UNALLOCATED 0 00011 SADDLV 0 01010 SMAXV 0 11010 SMINV 0 11011 ADDV 0 x0 01110 UNALLOCATED 0 00 01100 FMAXNMV Half-precision 0 00 01111 FMAXV Half-precision 0 10 01100 FMINNMV Half-precision 0 10 01111 FMINV Half-precision 1 00011 UADDLV 1 01010 UMAXV 1 11010 UMINV 1 11011 UNALLOCATED 0 1 x0 011x0 UNALLOCATED 0 1 x0 01111 UNALLOCATED 1 1 x0 01110 UNALLOCATED 1 1 00 01100 FMAXNMV Single-precision 1 1 00 01111 FMAXV Single-precision 1 1 10 01100 FMINNMV Single-precision 1 1 10 01111 FMINV Single-precision 0 0 1 1 1 0 0 0 0 0 1 Decode fields Instruction page Encoding Q op imm5 imm4 0 0000 DUP (element) Vector 0 0001 DUP (general) 0 01x0 UNALLOCATED 0 1xxx UNALLOCATED 0 0 001x UNALLOCATED 0 0 0101 SMOV 32-bit 0 0 0111 UMOV 32-bit 0 1 UNALLOCATED 1 0 0010 UNALLOCATED 1 0 0011 INS (general) 1 0 0101 SMOV 64-bit 1 0 x0xxx 0111 UNALLOCATED 1 0 x1000 0111 UMOV 64-bit 1 0 x1001 0111 UNALLOCATED 1 0 x101x 0111 UNALLOCATED 1 0 x11xx 0111 UNALLOCATED 1 1 INS (element) 0 1 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding op2 00 EXT != 00 UNALLOCATED 0 0 1 1 1 1 0 0 0 0 0 1 Decode fields Instruction page Encoding Q op cmode o2 0 0xx0 0 MOVI 32-bit shifted immediate 0 0xx1 0 ORR (vector, immediate) 32-bit 0 10x0 0 MOVI 16-bit shifted immediate 0 10x1 0 ORR (vector, immediate) 16-bit 0 110x 0 MOVI 32-bit shifting ones 0 1110 0 MOVI 8-bit 0 1111 0 FMOV (vector, immediate) Single-precision 0 1111 1 FMOV (vector, immediate) Half-precision 0 != 1111 1 UNALLOCATED 1 1 UNALLOCATED 1 0xx0 0 MVNI 32-bit shifted immediate 1 0xx1 0 BIC (vector, immediate) 32-bit 1 10x0 0 MVNI 16-bit shifted immediate 1 10x1 0 BIC (vector, immediate) 16-bit 1 110x 0 MVNI 32-bit shifting ones 0 1 1110 0 MOVI 64-bit scalar 0 1 1111 0 UNALLOCATED 1 1 1110 0 MOVI 64-bit vector 1 1 1111 0 FMOV (vector, immediate) Double-precision 0 0 0 1 1 1 0 0 0 1 0 Decode fields Instruction page Encoding opcode x00 UNALLOCATED 001 UZP1 010 TRN1 011 ZIP1 101 UZP2 110 TRN2 111 ZIP2 0 1 1 1 1 1 0 0 0 0 0 1 Decode fields Instruction page Encoding op imm4 0 0000 DUP (element) Scalar 0 != 0000 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 1 0 1 1 0 0 0 1 0 Decode fields Instruction page Encoding U size opcode x0xxx UNALLOCATED 01110 UNALLOCATED 111xx UNALLOCATED 10 01101 UNALLOCATED 0 x1 011x1 UNALLOCATED 0 x1 01100 UNALLOCATED 0 00 01100 FMAXNMP (scalar) Half-precision 0 00 01101 FADDP (scalar) Half-precision 0 00 01111 FMAXP (scalar) Half-precision 0 10 01100 FMINNMP (scalar) Half-precision 0 10 01111 FMINP (scalar) Half-precision 0 11 x100x UNALLOCATED 0 11 x1010 UNALLOCATED 0 11 01011 UNALLOCATED 0 11 11011 ADDP (scalar) 0 != 11 x10xx UNALLOCATED 1 x10xx UNALLOCATED 1 0x 01100 FMAXNMP (scalar) Single-precision and double-precision 1 0x 01101 FADDP (scalar) Single-precision and double-precision 1 0x 01111 FMAXP (scalar) Single-precision and double-precision 1 1x 01100 FMINNMP (scalar) Single-precision and double-precision 1 1x 01111 FMINP (scalar) Single-precision and double-precision 1 11 01101 UNALLOCATED 0 1 1 1 1 1 1 0 1 Decode fields Instruction page Encoding U immh opcode 0xxx1 UNALLOCATED 101xx UNALLOCATED 11101 UNALLOCATED 0xxx x10x0 UNALLOCATED 0xxx 00xx0 UNALLOCATED 0xxx 110x1 UNALLOCATED 0000 x1110 UNALLOCATED 0000 1001x UNALLOCATED 0000 11100 UNALLOCATED 0000 11111 UNALLOCATED 1xxx 110xx UNALLOCATED != 0000 11110 UNALLOCATED 0 01100 UNALLOCATED 0 1000x UNALLOCATED 0 1xxx 00000 SSHR Scalar 0 1xxx 00010 SSRA Scalar 0 1xxx 00100 SRSHR Scalar 0 1xxx 00110 SRSRA Scalar 0 1xxx 01000 UNALLOCATED 0 1xxx 01010 SHL Scalar 0 != 0000 01110 SQSHL (immediate) Scalar 0 != 0000 10010 SQSHRN, SQSHRN2 Scalar 0 != 0000 10011 SQRSHRN, SQRSHRN2 Scalar 0 != 0000 11100 SCVTF (vector, fixed-point) Scalar 0 != 0000 11111 FCVTZS (vector, fixed-point) Scalar 1 0000 01100 UNALLOCATED 1 0000 1000x UNALLOCATED 1 1xxx 00000 USHR Scalar 1 1xxx 00010 USRA Scalar 1 1xxx 00100 URSHR Scalar 1 1xxx 00110 URSRA Scalar 1 1xxx 01000 SRI Scalar 1 1xxx 01010 SLI Scalar 1 != 0000 01100 SQSHLU Scalar 1 != 0000 01110 UQSHL (immediate) Scalar 1 != 0000 10000 SQSHRUN, SQSHRUN2 Scalar 1 != 0000 10001 SQRSHRUN, SQRSHRUN2 Scalar 1 != 0000 10010 UQSHRN, UQSHRN2 Scalar 1 != 0000 10011 UQRSHRN, UQRSHRN2 Scalar 1 != 0000 11100 UCVTF (vector, fixed-point) Scalar 1 != 0000 11111 FCVTZU (vector, fixed-point) Scalar 0 1 1 1 1 1 0 1 0 0 Decode fields Instruction page Encoding U opcode 0 0xxx UNALLOCATED 0 1xx0 UNALLOCATED 0 1001 SQDMLAL, SQDMLAL2 (vector) Scalar 0 1011 SQDMLSL, SQDMLSL2 (vector) Scalar 0 1101 SQDMULL, SQDMULL2 (vector) Scalar 0 1111 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 1 0 1 1 Decode fields Instruction page Encoding U size opcode x0011 UNALLOCATED 011x1 UNALLOCATED 11001 UNALLOCATED 11110 UNALLOCATED x0 0x1x0 UNALLOCATED x1 00100 UNALLOCATED x1 011x0 UNALLOCATED 0x xx0x0 UNALLOCATED 0x 10x01 UNALLOCATED 01 00110 UNALLOCATED 1x 10010 UNALLOCATED 1x 11000 UNALLOCATED 10 0x0x0 UNALLOCATED 10 10x0x UNALLOCATED 11 00000 UNALLOCATED 11 00010 UNALLOCATED 11 10101 UNALLOCATED != 10 10100 UNALLOCATED != 11 00111 UNALLOCATED 0 00001 SQADD Scalar 0 00101 SQSUB Scalar 0 01001 SQSHL (register) Scalar 0 01011 SQRSHL Scalar 0 10110 SQDMULH (vector) Scalar 0 10111 UNALLOCATED 0 11101 UNALLOCATED 0 0x 11011 FMULX Scalar single-precision and double-precision 0 0x 11100 FCMEQ (register) Scalar single-precision and double-precision 0 0x 11111 FRECPS Scalar single-precision and double-precision 0 1x 11010 UNALLOCATED 0 1x 11011 UNALLOCATED 0 1x 11100 UNALLOCATED 0 1x 11111 FRSQRTS Scalar single-precision and double-precision 0 11 00110 CMGT (register) Scalar 0 11 00111 CMGE (register) Scalar 0 11 01000 SSHL Scalar 0 11 01010 SRSHL Scalar 0 11 10000 ADD (vector) Scalar 0 11 10001 CMTST Scalar 1 00001 UQADD Scalar 1 00101 UQSUB Scalar 1 01001 UQSHL (register) Scalar 1 01011 UQRSHL Scalar 1 1x111 UNALLOCATED 1 10110 SQRDMULH (vector) Scalar 1 11011 UNALLOCATED 1 0x 11100 FCMGE (register) Scalar single-precision and double-precision 1 0x 11101 FACGE Scalar single-precision and double-precision 1 1x 11010 FABD Scalar single-precision and double-precision 1 1x 11100 FCMGT (register) Scalar single-precision and double-precision 1 1x 11101 FACGT Scalar single-precision and double-precision 1 11 00110 CMHI (register) Scalar 1 11 00111 CMHS (register) Scalar 1 11 01000 USHL Scalar 1 11 01010 URSHL Scalar 1 11 10000 SUB (vector) Scalar 1 11 10001 CMEQ (register) Scalar 0 1 1 1 1 1 0 1 0 0 0 1 Decode fields Instruction page Encoding U a opcode 00x UNALLOCATED 0 010 UNALLOCATED 0 101 UNALLOCATED 0 0 011 FMULX Scalar half-precision 0 0 100 FCMEQ (register) Scalar half-precision 0 0 110 UNALLOCATED 0 0 111 FRECPS Scalar half-precision 0 1 x10 UNALLOCATED 0 1 011 UNALLOCATED 0 1 100 UNALLOCATED 0 1 111 FRSQRTS Scalar half-precision 1 011 UNALLOCATED 1 11x UNALLOCATED 1 0 100 FCMGE (register) Scalar half-precision 1 0 101 FACGE Scalar half-precision 1 1 010 FABD Scalar half-precision 1 1 100 FCMGT (register) Scalar half-precision 1 1 101 FACGT Scalar half-precision 0 1 1 1 1 1 0 0 1 1 Decode fields Instruction page Encoding U opcode 0 UNALLOCATED 1 0000 SQRDMLAH (vector) Scalar 1 0001 SQRDMLSH (vector) Scalar 1 001x UNALLOCATED 1 01xx UNALLOCATED 1 1xxx UNALLOCATED 0 1 1 1 1 1 0 1 0 0 0 0 1 0 Decode fields Instruction page Encoding U size opcode 00xx0 UNALLOCATED 00x01 UNALLOCATED 1x000 UNALLOCATED 10xx1 UNALLOCATED 11001 UNALLOCATED 0x 01xxx UNALLOCATED 0x 1111x UNALLOCATED 1x 01111 UNALLOCATED 1x 11100 UNALLOCATED 10 010x1 UNALLOCATED 10 01000 UNALLOCATED 0 00011 SUQADD Scalar 0 00111 SQABS Scalar 0 10010 UNALLOCATED 0 10100 SQXTN, SQXTN2 Scalar 0 10110 UNALLOCATED 0 0x 11010 FCVTNS (vector) Scalar single-precision and double-precision 0 0x 11011 FCVTMS (vector) Scalar single-precision and double-precision 0 0x 11100 FCVTAS (vector) Scalar single-precision and double-precision 0 0x 11101 SCVTF (vector, integer) Scalar single-precision and double-precision 0 1x 01100 FCMGT (zero) Scalar single-precision and double-precision 0 1x 01101 FCMEQ (zero) Scalar single-precision and double-precision 0 1x 01110 FCMLT (zero) Scalar single-precision and double-precision 0 1x 11010 FCVTPS (vector) Scalar single-precision and double-precision 0 1x 11011 FCVTZS (vector, integer) Scalar single-precision and double-precision 0 1x 11101 FRECPE Scalar single-precision and double-precision 0 1x 11110 UNALLOCATED 0 1x 11111 FRECPX Single-precision and double-precision 0 10 01010 UNALLOCATED 0 11 01000 CMGT (zero) Scalar 0 11 01001 CMEQ (zero) Scalar 0 11 01010 CMLT (zero) Scalar 0 11 01011 ABS Scalar 1 00011 USQADD Scalar 1 00111 SQNEG Scalar 1 10010 SQXTUN, SQXTUN2 Scalar 1 10100 UQXTN, UQXTN2 Scalar 1 0x 11010 FCVTNU (vector) Scalar single-precision and double-precision 1 0x 11011 FCVTMU (vector) Scalar single-precision and double-precision 1 0x 11100 FCVTAU (vector) Scalar single-precision and double-precision 1 0x 11101 UCVTF (vector, integer) Scalar single-precision and double-precision 1 00 10110 UNALLOCATED 1 01 10110 FCVTXN, FCVTXN2 Scalar 1 1x 01x10 UNALLOCATED 1 1x 01100 FCMGE (zero) Scalar single-precision and double-precision 1 1x 01101 FCMLE (zero) Scalar single-precision and double-precision 1 1x 1x110 UNALLOCATED 1 1x 11010 FCVTPU (vector) Scalar single-precision and double-precision 1 1x 11011 FCVTZU (vector, integer) Scalar single-precision and double-precision 1 1x 11101 FRSQRTE Scalar single-precision and double-precision 1 1x 11111 UNALLOCATED 1 11 01000 CMGE (zero) Scalar 1 11 01001 CMLE (zero) Scalar 1 11 01011 NEG (vector) Scalar 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 Decode fields Instruction page Encoding U a opcode x0xxx UNALLOCATED 1100x UNALLOCATED 0 01xxx UNALLOCATED 1 010xx UNALLOCATED 1 11100 UNALLOCATED 0 0 11010 FCVTNS (vector) Scalar half-precision 0 0 11011 FCVTMS (vector) Scalar half-precision 0 0 11100 FCVTAS (vector) Scalar half-precision 0 0 11101 SCVTF (vector, integer) Scalar half-precision 0 0 1111x UNALLOCATED 0 1 01100 FCMGT (zero) Scalar half-precision 0 1 01101 FCMEQ (zero) Scalar half-precision 0 1 01110 FCMLT (zero) Scalar half-precision 0 1 01111 UNALLOCATED 0 1 11010 FCVTPS (vector) Scalar half-precision 0 1 11011 FCVTZS (vector, integer) Scalar half-precision 0 1 11101 FRECPE Scalar half-precision 0 1 11110 UNALLOCATED 0 1 11111 FRECPX Half-precision 1 1111x UNALLOCATED 1 0 11010 FCVTNU (vector) Scalar half-precision 1 0 11011 FCVTMU (vector) Scalar half-precision 1 0 11100 FCVTAU (vector) Scalar half-precision 1 0 11101 UCVTF (vector, integer) Scalar half-precision 1 1 01100 FCMGE (zero) Scalar half-precision 1 1 01101 FCMLE (zero) Scalar half-precision 1 1 0111x UNALLOCATED 1 1 11010 FCVTPU (vector) Scalar half-precision 1 1 11011 FCVTZU (vector, integer) Scalar half-precision 1 1 11101 FRSQRTE Scalar half-precision 0 1 1 1 1 1 1 0 Decode fields Instruction page Encoding U size opcode 01 1001 UNALLOCATED 0 0xx0 UNALLOCATED 0 0011 SQDMLAL, SQDMLAL2 (by element) Scalar 0 0111 SQDMLSL, SQDMLSL2 (by element) Scalar 0 10x0 UNALLOCATED 0 1011 SQDMULL, SQDMULL2 (by element) Scalar 0 1100 SQDMULH (by element) Scalar 0 1101 SQRDMULH (by element) Scalar 0 111x UNALLOCATED 0 00 0001 FMLA (by element) Scalar, half-precision 0 00 0101 FMLS (by element) Scalar, half-precision 0 00 1001 FMUL (by element) Scalar, half-precision 0 01 0x01 UNALLOCATED 0 1x 0001 FMLA (by element) Scalar, single-precision and double-precision 0 1x 0101 FMLS (by element) Scalar, single-precision and double-precision 0 1x 1001 FMUL (by element) Scalar, single-precision and double-precision 1 0xxx UNALLOCATED 1 1xx0 UNALLOCATED 1 1011 UNALLOCATED 1 1101 SQRDMLAH (by element) Scalar 1 1111 SQRDMLSH (by element) Scalar 1 00 1001 FMULX (by element) Scalar, half-precision 1 1x 1001 FMULX (by element) Scalar, single-precision and double-precision 0 0 1 1 1 1 0 != 0000 1 Decode fields Instruction page Encoding U immh opcode != 0000 0xxx1 UNALLOCATED != 0000 1x110 UNALLOCATED != 0000 101x1 UNALLOCATED != 0000 110xx UNALLOCATED != 0000 11101 UNALLOCATED 0 != 0000 00000 SSHR Vector 0 != 0000 00010 SSRA Vector 0 != 0000 00100 SRSHR Vector 0 != 0000 00110 SRSRA Vector 0 != 0000 01x00 UNALLOCATED 0 != 0000 01010 SHL Vector 0 != 0000 01110 SQSHL (immediate) Vector 0 != 0000 10000 SHRN, SHRN2 0 != 0000 10001 RSHRN, RSHRN2 0 != 0000 10010 SQSHRN, SQSHRN2 Vector 0 != 0000 10011 SQRSHRN, SQRSHRN2 Vector 0 != 0000 10100 SSHLL, SSHLL2 0 != 0000 11100 SCVTF (vector, fixed-point) Vector 0 != 0000 11111 FCVTZS (vector, fixed-point) Vector 1 != 0000 00000 USHR Vector 1 != 0000 00010 USRA Vector 1 != 0000 00100 URSHR Vector 1 != 0000 00110 URSRA Vector 1 != 0000 01000 SRI Vector 1 != 0000 01010 SLI Vector 1 != 0000 01100 SQSHLU Vector 1 != 0000 01110 UQSHL (immediate) Vector 1 != 0000 10000 SQSHRUN, SQSHRUN2 Vector 1 != 0000 10001 SQRSHRUN, SQRSHRUN2 Vector 1 != 0000 10010 UQSHRN, UQSHRN2 Vector 1 != 0000 10011 UQRSHRN, UQRSHRN2 Vector 1 != 0000 10100 USHLL, USHLL2 1 != 0000 11100 UCVTF (vector, fixed-point) Vector 1 != 0000 11111 FCVTZU (vector, fixed-point) Vector 0 0 0 1 1 1 0 0 0 0 0 Decode fields Instruction page Encoding Q op2 len op 00 00 0 TBL Single register table 00 00 1 TBX Single register table 00 01 0 TBL Two register table 00 01 1 TBX Two register table 00 10 0 TBL Three register table 00 10 1 TBX Three register table 00 11 0 TBL Four register table 00 11 1 TBX Four register table 0 != 00 UNALLOCATED 1 01 1 LUTI4 Halfword 1 01 x0 0 UNALLOCATED 1 01 x1 0 LUTI4 Byte 1 10 0 UNALLOCATED 1 10 1 LUTI2 Byte 1 11 LUTI2 Halfword 0 0 1 1 1 0 1 0 0 Decode fields Instruction page Encoding U opcode 0 0000 SADDL, SADDL2 0 0001 SADDW, SADDW2 0 0010 SSUBL, SSUBL2 0 0011 SSUBW, SSUBW2 0 0100 ADDHN, ADDHN2 0 0101 SABAL, SABAL2 0 0110 SUBHN, SUBHN2 0 0111 SABDL, SABDL2 0 1000 SMLAL, SMLAL2 (vector) 0 1001 SQDMLAL, SQDMLAL2 (vector) Vector 0 1010 SMLSL, SMLSL2 (vector) 0 1011 SQDMLSL, SQDMLSL2 (vector) Vector 0 1100 SMULL, SMULL2 (vector) 0 1101 SQDMULL, SQDMULL2 (vector) Vector 0 1110 PMULL, PMULL2 0 1111 UNALLOCATED 1 0000 UADDL, UADDL2 1 0001 UADDW, UADDW2 1 0010 USUBL, USUBL2 1 0011 USUBW, USUBW2 1 0100 RADDHN, RADDHN2 1 0101 UABAL, UABAL2 1 0110 RSUBHN, RSUBHN2 1 0111 UABDL, UABDL2 1 1xx1 UNALLOCATED 1 1000 UMLAL, UMLAL2 (vector) 1 1010 UMLSL, UMLSL2 (vector) 1 1100 UMULL, UMULL2 (vector) 1 1110 UNALLOCATED 0 0 1 1 1 0 1 1 Decode fields Instruction page Encoding U size opcode 0 00000 SHADD 0 00001 SQADD Vector 0 00010 SRHADD 0 00100 SHSUB 0 00101 SQSUB Vector 0 00110 CMGT (register) Vector 0 00111 CMGE (register) Vector 0 01000 SSHL Vector 0 01001 SQSHL (register) Vector 0 01010 SRSHL Vector 0 01011 SQRSHL Vector 0 01100 SMAX 0 01101 SMIN 0 01110 SABD 0 01111 SABA 0 10000 ADD (vector) Vector 0 10001 CMTST Vector 0 10010 MLA (vector) 0 10011 MUL (vector) 0 10100 SMAXP 0 10101 SMINP 0 10110 SQDMULH (vector) Vector 0 10111 ADDP (vector) 0 x1 11101 UNALLOCATED 0 0x 11000 FMAXNM (vector) Single-precision and double-precision 0 0x 11001 FMLA (vector) Single-precision and double-precision 0 0x 11010 FADD (vector) Single-precision and double-precision 0 0x 11011 FMULX Vector single-precision and double-precision 0 0x 11100 FCMEQ (register) Vector single-precision and double-precision 0 0x 11110 FMAX (vector) Single-precision and double-precision 0 0x 11111 FRECPS Vector single-precision and double-precision 0 00 00011 AND (vector) 0 00 11101 FMLAL, FMLAL2 (vector) FMLAL 0 01 00011 BIC (vector, register) 0 1x 11000 FMINNM (vector) Single-precision and double-precision 0 1x 11001 FMLS (vector) Single-precision and double-precision 0 1x 11010 FSUB (vector) Single-precision and double-precision 0 1x 11011 FAMAX Single-precision and double-precision 0 1x 11100 UNALLOCATED 0 1x 11110 FMIN (vector) Single-precision and double-precision 0 1x 11111 FRSQRTS Vector single-precision and double-precision 0 10 00011 ORR (vector, register) 0 10 11101 FMLSL, FMLSL2 (vector) FMLSL 0 11 00011 ORN (vector) 1 00000 UHADD 1 00001 UQADD Vector 1 00010 URHADD 1 00100 UHSUB 1 00101 UQSUB Vector 1 00110 CMHI (register) Vector 1 00111 CMHS (register) Vector 1 01000 USHL Vector 1 01001 UQSHL (register) Vector 1 01010 URSHL Vector 1 01011 UQRSHL Vector 1 01100 UMAX 1 01101 UMIN 1 01110 UABD 1 01111 UABA 1 10000 SUB (vector) Vector 1 10001 CMEQ (register) Vector 1 10010 MLS (vector) 1 10011 PMUL 1 10100 UMAXP 1 10101 UMINP 1 10110 SQRDMULH (vector) Vector 1 10111 UNALLOCATED 1 x1 11001 UNALLOCATED 1 0x 11000 FMAXNMP (vector) Single-precision and double-precision 1 0x 11010 FADDP (vector) Single-precision and double-precision 1 0x 11011 FMUL (vector) Single-precision and double-precision 1 0x 11100 FCMGE (register) Vector single-precision and double-precision 1 0x 11101 FACGE Vector single-precision and double-precision 1 0x 11110 FMAXP (vector) Single-precision and double-precision 1 0x 11111 FDIV (vector) Single-precision and double-precision 1 00 00011 EOR (vector) 1 00 11001 FMLAL, FMLAL2 (vector) FMLAL2 1 01 00011 BSL 1 1x 11000 FMINNMP (vector) Single-precision and double-precision 1 1x 11010 FABD Vector single-precision and double-precision 1 1x 11011 FAMIN Single-precision and double-precision 1 1x 11100 FCMGT (register) Vector single-precision and double-precision 1 1x 11101 FACGT Vector single-precision and double-precision 1 1x 11110 FMINP (vector) Single-precision and double-precision 1 1x 11111 FSCALE Single-precision and double-precision 1 10 00011 BIT 1 10 11001 FMLSL, FMLSL2 (vector) FMLSL2 1 11 00011 BIF 0 0 1 1 1 0 1 0 0 0 1 Decode fields Instruction page Encoding U a opcode 0 0 000 FMAXNM (vector) Half-precision 0 0 001 FMLA (vector) Half-precision 0 0 010 FADD (vector) Half-precision 0 0 011 FMULX Vector half-precision 0 0 100 FCMEQ (register) Vector half-precision 0 0 101 UNALLOCATED 0 0 110 FMAX (vector) Half-precision 0 0 111 FRECPS Vector half-precision 0 1 000 FMINNM (vector) Half-precision 0 1 001 FMLS (vector) Half-precision 0 1 010 FSUB (vector) Half-precision 0 1 011 FAMAX Half-precision 0 1 10x UNALLOCATED 0 1 110 FMIN (vector) Half-precision 0 1 111 FRSQRTS Vector half-precision 1 001 UNALLOCATED 1 0 000 FMAXNMP (vector) Half-precision 1 0 010 FADDP (vector) Half-precision 1 0 011 FMUL (vector) Half-precision 1 0 100 FCMGE (register) Vector half-precision 1 0 101 FACGE Vector half-precision 1 0 110 FMAXP (vector) Half-precision 1 0 111 FDIV (vector) Half-precision 1 1 000 FMINNMP (vector) Half-precision 1 1 010 FABD Vector half-precision 1 1 011 FAMIN Half-precision 1 1 100 FCMGT (register) Vector half-precision 1 1 101 FACGT Vector half-precision 1 1 110 FMINP (vector) Half-precision 1 1 111 FSCALE Half-precision 0 0 1 1 1 0 0 1 1 Decode fields Instruction page Encoding Q U size opcode 0 0000 UNALLOCATED 0 0010 SDOT (vector) 0 0x 1010 UNALLOCATED 0 0x 1100 UNALLOCATED 0 00 1110 FCVTN, FCVTN2 (single-precision to 8-bit floating-point) 0 00 1111 FDOT (8-bit floating-point to single-precision, vector) 0 01 1110 FCVTN (half-precision to 8-bit floating-point) 0 01 1111 FDOT (8-bit floating-point to half-precision, vector) 0 10 0001 UNALLOCATED 0 10 0011 USDOT (vector) 0 10 1xx0 UNALLOCATED 0 10 1x11 UNALLOCATED 0 10 1001 UNALLOCATED 0 11 1xx0 UNALLOCATED 0 != 10 x0x1 UNALLOCATED 1 0000 SQRDMLAH (vector) Vector 1 0001 SQRDMLSH (vector) Vector 1 0010 UDOT (vector) 1 0011 UNALLOCATED 1 10xx FCMLA 1 11x0 FCADD 1 x0 1111 UNALLOCATED 1 01 1111 BFDOT (vector) 1 11 1111 BFMLALB, BFMLALT (vector) 0 01xx UNALLOCATED 0 1101 UNALLOCATED 0 0 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) FMLALLBB 0 0 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) FMLALLBT 0 0 11 1111 FMLALB, FMLALT (vector) FMLALB 1 10 011x UNALLOCATED 1 != 10 01xx UNALLOCATED 1 0 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) FMLALLTB 1 0 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector) FMLALLTT 1 0 10 0100 SMMLA (vector) 1 0 10 0101 USMMLA (vector) 1 0 11 1101 UNALLOCATED 1 0 11 1111 FMLALB, FMLALT (vector) FMLALT 1 0 != 11 1101 UNALLOCATED 1 1 00 1101 FMMLA (widening, 8-bit floating-point to half-precision) 1 1 01 1101 BFMMLA (widening) 1 1 10 0100 UMMLA (vector) 1 1 10 0101 UNALLOCATED 1 1 10 1101 FMMLA (widening, 8-bit floating-point to single-precision) 1 1 11 1101 UNALLOCATED 0 0 1 1 1 0 1 0 0 0 0 1 0 Decode fields Instruction page Encoding U size opcode 1000x UNALLOCATED 10101 UNALLOCATED 0x 011xx UNALLOCATED 10 11110 UNALLOCATED 11 1x110 UNALLOCATED 0 00000 REV64 0 00001 REV16 (vector) 0 00010 SADDLP 0 00011 SUQADD Vector 0 00100 CLS (vector) 0 00101 CNT 0 00110 SADALP 0 00111 SQABS Vector 0 01000 CMGT (zero) Vector 0 01001 CMEQ (zero) Vector 0 01010 CMLT (zero) Vector 0 01011 ABS Vector 0 10010 XTN, XTN2 0 10011 UNALLOCATED 0 10100 SQXTN, SQXTN2 Vector 0 0x 10110 FCVTN, FCVTN2 (double to single-precision, single to half-precision) 0 0x 10111 FCVTL, FCVTL2 0 0x 11000 FRINTN (vector) Single-precision and double-precision 0 0x 11001 FRINTM (vector) Single-precision and double-precision 0 0x 11010 FCVTNS (vector) Vector single-precision and double-precision 0 0x 11011 FCVTMS (vector) Vector single-precision and double-precision 0 0x 11100 FCVTAS (vector) Vector single-precision and double-precision 0 0x 11101 SCVTF (vector, integer) Vector single-precision and double-precision 0 0x 11110 FRINT32Z (vector) 0 0x 11111 FRINT64Z (vector) 0 1x 01100 FCMGT (zero) Vector single-precision and double-precision 0 1x 01101 FCMEQ (zero) Vector single-precision and double-precision 0 1x 01110 FCMLT (zero) Vector single-precision and double-precision 0 1x 01111 FABS (vector) Single-precision and double-precision 0 1x 1x111 UNALLOCATED 0 1x 11000 FRINTP (vector) Single-precision and double-precision 0 1x 11001 FRINTZ (vector) Single-precision and double-precision 0 1x 11010 FCVTPS (vector) Vector single-precision and double-precision 0 1x 11011 FCVTZS (vector, integer) Vector single-precision and double-precision 0 1x 11100 URECPE 0 1x 11101 FRECPE Vector single-precision and double-precision 0 10 10110 BFCVTN, BFCVTN2 1 00000 REV32 (vector) 1 00010 UADDLP 1 00011 USQADD Vector 1 00100 CLZ (vector) 1 00110 UADALP 1 00111 SQNEG Vector 1 01000 CMGE (zero) Vector 1 01001 CMLE (zero) Vector 1 01010 UNALLOCATED 1 01011 NEG (vector) Vector 1 10010 SQXTUN, SQXTUN2 Vector 1 10011 SHLL, SHLL2 1 10100 UQXTN, UQXTN2 Vector 1 x0 10110 UNALLOCATED 1 0x 00001 UNALLOCATED 1 0x 11000 FRINTA (vector) Single-precision and double-precision 1 0x 11001 FRINTX (vector) Single-precision and double-precision 1 0x 11010 FCVTNU (vector) Vector single-precision and double-precision 1 0x 11011 FCVTMU (vector) Vector single-precision and double-precision 1 0x 11100 FCVTAU (vector) Vector single-precision and double-precision 1 0x 11101 UCVTF (vector, integer) Vector single-precision and double-precision 1 0x 11110 FRINT32X (vector) 1 0x 11111 FRINT64X (vector) 1 00 00101 NOT 1 00 10111 F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 F1CVTL{2} 1 01 00101 RBIT (vector) 1 01 10110 FCVTXN, FCVTXN2 Vector 1 01 10111 F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 F2CVTL{2} 1 1x 00x01 UNALLOCATED 1 1x 01100 FCMGE (zero) Vector single-precision and double-precision 1 1x 01101 FCMLE (zero) Vector single-precision and double-precision 1 1x 01110 UNALLOCATED 1 1x 01111 FNEG (vector) Single-precision and double-precision 1 1x 11000 UNALLOCATED 1 1x 11001 FRINTI (vector) Single-precision and double-precision 1 1x 11010 FCVTPU (vector) Vector single-precision and double-precision 1 1x 11011 FCVTZU (vector, integer) Vector single-precision and double-precision 1 1x 11100 URSQRTE 1 1x 11101 FRSQRTE Vector single-precision and double-precision 1 1x 11111 FSQRT (vector) Single-precision and double-precision 1 10 10111 BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 BF1CVTL{2} 1 11 10111 BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 BF2CVTL{2} 0 0 1 1 1 0 1 1 1 1 0 0 1 0 Decode fields Instruction page Encoding U a opcode x0xxx UNALLOCATED 0 01xxx UNALLOCATED 0 1111x UNALLOCATED 1 010xx UNALLOCATED 1 11100 UNALLOCATED 0 0 11000 FRINTN (vector) Half-precision 0 0 11001 FRINTM (vector) Half-precision 0 0 11010 FCVTNS (vector) Vector half-precision 0 0 11011 FCVTMS (vector) Vector half-precision 0 0 11100 FCVTAS (vector) Vector half-precision 0 0 11101 SCVTF (vector, integer) Vector half-precision 0 1 01100 FCMGT (zero) Vector half-precision 0 1 01101 FCMEQ (zero) Vector half-precision 0 1 01110 FCMLT (zero) Vector half-precision 0 1 01111 FABS (vector) Half-precision 0 1 11000 FRINTP (vector) Half-precision 0 1 11001 FRINTZ (vector) Half-precision 0 1 11010 FCVTPS (vector) Vector half-precision 0 1 11011 FCVTZS (vector, integer) Vector half-precision 0 1 11101 FRECPE Vector half-precision 0 1 1111x UNALLOCATED 1 0 11000 FRINTA (vector) Half-precision 1 0 11001 FRINTX (vector) Half-precision 1 0 11010 FCVTNU (vector) Vector half-precision 1 0 11011 FCVTMU (vector) Vector half-precision 1 0 11100 FCVTAU (vector) Vector half-precision 1 0 11101 UCVTF (vector, integer) Vector half-precision 1 1 x1110 UNALLOCATED 1 1 01100 FCMGE (zero) Vector half-precision 1 1 01101 FCMLE (zero) Vector half-precision 1 1 01111 FNEG (vector) Half-precision 1 1 11000 UNALLOCATED 1 1 11001 FRINTI (vector) Half-precision 1 1 11010 FCVTPU (vector) Vector half-precision 1 1 11011 FCVTZU (vector, integer) Vector half-precision 1 1 11101 FRSQRTE Vector half-precision 1 1 11111 FSQRT (vector) Half-precision 0 0 1 1 1 1 0 Decode fields Instruction page Encoding Q U size opcode 01 1001 UNALLOCATED 0 0010 SMLAL, SMLAL2 (by element) 0 0011 SQDMLAL, SQDMLAL2 (by element) Vector 0 0110 SMLSL, SMLSL2 (by element) 0 0111 SQDMLSL, SQDMLSL2 (by element) Vector 0 1000 MUL (by element) 0 1010 SMULL, SMULL2 (by element) 0 1011 SQDMULL, SQDMULL2 (by element) Vector 0 1100 SQDMULH (by element) Vector 0 1101 SQRDMULH (by element) Vector 0 1110 SDOT (by element) 0 00 0000 FDOT (8-bit floating-point to single-precision, by element) 0 00 0001 FMLA (by element) Vector, half-precision 0 00 0101 FMLS (by element) Vector, half-precision 0 00 1001 FMUL (by element) Vector, half-precision 0 00 1111 SUDOT (by element) 0 01 0x01 UNALLOCATED 0 01 0000 FDOT (8-bit floating-point to half-precision, by element) 0 01 1111 BFDOT (by element) 0 1x 0001 FMLA (by element) Vector, single-precision and double-precision 0 1x 0101 FMLS (by element) Vector, single-precision and double-precision 0 1x 1001 FMUL (by element) Vector, single-precision and double-precision 0 10 0000 FMLAL, FMLAL2 (by element) FMLAL 0 10 0100 FMLSL, FMLSL2 (by element) FMLSL 0 10 1111 USDOT (by element) 0 11 1111 BFMLALB, BFMLALT (by element) 0 != 10 0100 UNALLOCATED 1 0xx1 FCMLA (by element) 1 0000 MLA (by element) 1 0010 UMLAL, UMLAL2 (by element) 1 0100 MLS (by element) 1 0110 UMLSL, UMLSL2 (by element) 1 1010 UMULL, UMULL2 (by element) 1 1011 UNALLOCATED 1 1101 SQRDMLAH (by element) Vector 1 1110 UDOT (by element) 1 1111 SQRDMLSH (by element) Vector 1 0x 1100 UNALLOCATED 1 00 1001 FMULX (by element) Vector, half-precision 1 1x 1001 FMULX (by element) Vector, single-precision and double-precision 1 10 1000 FMLAL, FMLAL2 (by element) FMLAL2 1 10 1100 FMLSL, FMLSL2 (by element) FMLSL2 1 11 1x00 UNALLOCATED 0 0 11 0000 FMLALB, FMLALT (by element) FMLALB 0 1 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) FMLALLBB 0 1 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) FMLALLBT 1 0 11 0000 FMLALB, FMLALT (by element) FMLALT 1 1 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) FMLALLTB 1 1 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element) FMLALLTT 0 1 1 1 1 0 0 Decode fields Instruction page Encoding sf S ftype rmode opcode 0 1xx UNALLOCATED 0 10 0xx UNALLOCATED 0 != 10 x1 01x UNALLOCATED 0 != 10 0x 00x UNALLOCATED 0 != 10 10 0xx UNALLOCATED 1 UNALLOCATED 0 0 00 00 010 SCVTF (scalar, fixed-point) 32-bit to single-precision 0 0 00 00 011 UCVTF (scalar, fixed-point) 32-bit to single-precision 0 0 00 11 000 FCVTZS (scalar, fixed-point) Single-precision to 32-bit 0 0 00 11 001 FCVTZU (scalar, fixed-point) Single-precision to 32-bit 0 0 01 00 010 SCVTF (scalar, fixed-point) 32-bit to double-precision 0 0 01 00 011 UCVTF (scalar, fixed-point) 32-bit to double-precision 0 0 01 11 000 FCVTZS (scalar, fixed-point) Double-precision to 32-bit 0 0 01 11 001 FCVTZU (scalar, fixed-point) Double-precision to 32-bit 0 0 11 00 010 SCVTF (scalar, fixed-point) 32-bit to half-precision 0 0 11 00 011 UCVTF (scalar, fixed-point) 32-bit to half-precision 0 0 11 11 000 FCVTZS (scalar, fixed-point) Half-precision to 32-bit 0 0 11 11 001 FCVTZU (scalar, fixed-point) Half-precision to 32-bit 1 0 00 00 010 SCVTF (scalar, fixed-point) 64-bit to single-precision 1 0 00 00 011 UCVTF (scalar, fixed-point) 64-bit to single-precision 1 0 00 11 000 FCVTZS (scalar, fixed-point) Single-precision to 64-bit 1 0 00 11 001 FCVTZU (scalar, fixed-point) Single-precision to 64-bit 1 0 01 00 010 SCVTF (scalar, fixed-point) 64-bit to double-precision 1 0 01 00 011 UCVTF (scalar, fixed-point) 64-bit to double-precision 1 0 01 11 000 FCVTZS (scalar, fixed-point) Double-precision to 64-bit 1 0 01 11 001 FCVTZU (scalar, fixed-point) Double-precision to 64-bit 1 0 11 00 010 SCVTF (scalar, fixed-point) 64-bit to half-precision 1 0 11 00 011 UCVTF (scalar, fixed-point) 64-bit to half-precision 1 0 11 11 000 FCVTZS (scalar, fixed-point) Half-precision to 64-bit 1 0 11 11 001 FCVTZU (scalar, fixed-point) Half-precision to 64-bit 0 1 1 1 1 0 1 0 0 0 0 0 0 Decode fields Instruction page Encoding sf S ftype rmode opcode 0 10 x0 UNALLOCATED 0 10 x1 0xx UNALLOCATED 0 10 x1 10x UNALLOCATED 0 11 x1 11x UNALLOCATED 0 != 10 01 10x UNALLOCATED 1 UNALLOCATED 0 0 x0 01 11x UNALLOCATED 0 0 00 00 000 FCVTNS (scalar) Single-precision to 32-bit 0 0 00 00 001 FCVTNU (scalar) Single-precision to 32-bit 0 0 00 00 010 SCVTF (scalar, integer) 32-bit to single-precision 0 0 00 00 011 UCVTF (scalar, integer) 32-bit to single-precision 0 0 00 00 100 FCVTAS (scalar) Single-precision to 32-bit 0 0 00 00 101 FCVTAU (scalar) Single-precision to 32-bit 0 0 00 00 110 FMOV (general) Single-precision to 32-bit 0 0 00 00 111 FMOV (general) 32-bit to single-precision 0 0 00 01 000 FCVTPS (scalar) Single-precision to 32-bit 0 0 00 01 001 FCVTPU (scalar) Single-precision to 32-bit 0 0 00 1x 1xx UNALLOCATED 0 0 00 10 000 FCVTMS (scalar) Single-precision to 32-bit 0 0 00 10 001 FCVTMU (scalar) Single-precision to 32-bit 0 0 00 11 000 FCVTZS (scalar, integer) Single-precision to 32-bit 0 0 00 11 001 FCVTZU (scalar, integer) Single-precision to 32-bit 0 0 00 != 00 01x UNALLOCATED 0 0 01 0x 11x UNALLOCATED 0 0 01 00 000 FCVTNS (scalar) Double-precision to 32-bit 0 0 01 00 001 FCVTNU (scalar) Double-precision to 32-bit 0 0 01 00 010 SCVTF (scalar, integer) 32-bit to double-precision 0 0 01 00 011 UCVTF (scalar, integer) 32-bit to double-precision 0 0 01 00 100 FCVTAS (scalar) Double-precision to 32-bit 0 0 01 00 101 FCVTAU (scalar) Double-precision to 32-bit 0 0 01 01 000 FCVTPS (scalar) Double-precision to 32-bit 0 0 01 01 001 FCVTPU (scalar) Double-precision to 32-bit 0 0 01 01 010 FCVTNS (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 01 011 FCVTNU (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 10 000 FCVTMS (scalar) Double-precision to 32-bit 0 0 01 10 001 FCVTMU (scalar) Double-precision to 32-bit 0 0 01 10 010 FCVTPS (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 10 011 FCVTPU (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 10 100 FCVTMS (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 10 101 FCVTMU (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 10 110 FCVTZS (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 10 111 FCVTZU (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 11 000 FCVTZS (scalar, integer) Double-precision to 32-bit 0 0 01 11 001 FCVTZU (scalar, integer) Double-precision to 32-bit 0 0 01 11 010 FCVTAS (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 11 011 FCVTAU (scalar SIMD&FP) Double-precision to 32-bit 0 0 01 11 100 SCVTF (scalar SIMD&FP) 32-bit to double-precision 0 0 01 11 101 UCVTF (scalar SIMD&FP) 32-bit to double-precision 0 0 01 11 110 FJCVTZS 0 0 01 11 111 UNALLOCATED 0 0 10 11 11x UNALLOCATED 0 0 11 00 000 FCVTNS (scalar) Half-precision to 32-bit 0 0 11 00 001 FCVTNU (scalar) Half-precision to 32-bit 0 0 11 00 010 SCVTF (scalar, integer) 32-bit to half-precision 0 0 11 00 011 UCVTF (scalar, integer) 32-bit to half-precision 0 0 11 00 100 FCVTAS (scalar) Half-precision to 32-bit 0 0 11 00 101 FCVTAU (scalar) Half-precision to 32-bit 0 0 11 00 110 FMOV (general) Half-precision to 32-bit 0 0 11 00 111 FMOV (general) 32-bit to half-precision 0 0 11 01 000 FCVTPS (scalar) Half-precision to 32-bit 0 0 11 01 001 FCVTPU (scalar) Half-precision to 32-bit 0 0 11 01 010 FCVTNS (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 01 011 FCVTNU (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 10 000 FCVTMS (scalar) Half-precision to 32-bit 0 0 11 10 001 FCVTMU (scalar) Half-precision to 32-bit 0 0 11 10 010 FCVTPS (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 10 011 FCVTPU (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 10 100 FCVTMS (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 10 101 FCVTMU (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 10 110 FCVTZS (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 10 111 FCVTZU (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 11 000 FCVTZS (scalar, integer) Half-precision to 32-bit 0 0 11 11 001 FCVTZU (scalar, integer) Half-precision to 32-bit 0 0 11 11 010 FCVTAS (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 11 011 FCVTAU (scalar SIMD&FP) Half-precision to 32-bit 0 0 11 11 100 SCVTF (scalar SIMD&FP) 32-bit to half-precision 0 0 11 11 101 UCVTF (scalar SIMD&FP) 32-bit to half-precision 1 0 x0 11 11x UNALLOCATED 1 0 00 0x 11x UNALLOCATED 1 0 00 00 000 FCVTNS (scalar) Single-precision to 64-bit 1 0 00 00 001 FCVTNU (scalar) Single-precision to 64-bit 1 0 00 00 010 SCVTF (scalar, integer) 64-bit to single-precision 1 0 00 00 011 UCVTF (scalar, integer) 64-bit to single-precision 1 0 00 00 100 FCVTAS (scalar) Single-precision to 64-bit 1 0 00 00 101 FCVTAU (scalar) Single-precision to 64-bit 1 0 00 01 000 FCVTPS (scalar) Single-precision to 64-bit 1 0 00 01 001 FCVTPU (scalar) Single-precision to 64-bit 1 0 00 01 010 FCVTNS (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 01 011 FCVTNU (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 10 000 FCVTMS (scalar) Single-precision to 64-bit 1 0 00 10 001 FCVTMU (scalar) Single-precision to 64-bit 1 0 00 10 010 FCVTPS (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 10 011 FCVTPU (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 10 100 FCVTMS (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 10 101 FCVTMU (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 10 110 FCVTZS (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 10 111 FCVTZU (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 11 000 FCVTZS (scalar, integer) Single-precision to 64-bit 1 0 00 11 001 FCVTZU (scalar, integer) Single-precision to 64-bit 1 0 00 11 010 FCVTAS (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 11 011 FCVTAU (scalar SIMD&FP) Single-precision to 64-bit 1 0 00 11 100 SCVTF (scalar SIMD&FP) 64-bit to single-precision 1 0 00 11 101 UCVTF (scalar SIMD&FP) 64-bit to single-precision 1 0 01 00 000 FCVTNS (scalar) Double-precision to 64-bit 1 0 01 00 001 FCVTNU (scalar) Double-precision to 64-bit 1 0 01 00 010 SCVTF (scalar, integer) 64-bit to double-precision 1 0 01 00 011 UCVTF (scalar, integer) 64-bit to double-precision 1 0 01 00 100 FCVTAS (scalar) Double-precision to 64-bit 1 0 01 00 101 FCVTAU (scalar) Double-precision to 64-bit 1 0 01 00 110 FMOV (general) Double-precision to 64-bit 1 0 01 00 111 FMOV (general) 64-bit to double-precision 1 0 01 01 x1x UNALLOCATED 1 0 01 01 000 FCVTPS (scalar) Double-precision to 64-bit 1 0 01 01 001 FCVTPU (scalar) Double-precision to 64-bit 1 0 01 1x 01x UNALLOCATED 1 0 01 1x 1xx UNALLOCATED 1 0 01 10 000 FCVTMS (scalar) Double-precision to 64-bit 1 0 01 10 001 FCVTMU (scalar) Double-precision to 64-bit 1 0 01 11 000 FCVTZS (scalar, integer) Double-precision to 64-bit 1 0 01 11 001 FCVTZU (scalar, integer) Double-precision to 64-bit 1 0 10 01 110 FMOV (general) Top half of 128-bit to 64-bit 1 0 10 01 111 FMOV (general) 64-bit to top half of 128-bit 1 0 11 00 000 FCVTNS (scalar) Half-precision to 64-bit 1 0 11 00 001 FCVTNU (scalar) Half-precision to 64-bit 1 0 11 00 010 SCVTF (scalar, integer) 64-bit to half-precision 1 0 11 00 011 UCVTF (scalar, integer) 64-bit to half-precision 1 0 11 00 100 FCVTAS (scalar) Half-precision to 64-bit 1 0 11 00 101 FCVTAU (scalar) Half-precision to 64-bit 1 0 11 00 110 FMOV (general) Half-precision to 64-bit 1 0 11 00 111 FMOV (general) 64-bit to half-precision 1 0 11 01 000 FCVTPS (scalar) Half-precision to 64-bit 1 0 11 01 001 FCVTPU (scalar) Half-precision to 64-bit 1 0 11 01 010 FCVTNS (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 01 011 FCVTNU (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 10 000 FCVTMS (scalar) Half-precision to 64-bit 1 0 11 10 001 FCVTMU (scalar) Half-precision to 64-bit 1 0 11 10 010 FCVTPS (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 10 011 FCVTPU (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 10 100 FCVTMS (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 10 101 FCVTMU (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 10 110 FCVTZS (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 10 111 FCVTZU (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 11 000 FCVTZS (scalar, integer) Half-precision to 64-bit 1 0 11 11 001 FCVTZU (scalar, integer) Half-precision to 64-bit 1 0 11 11 010 FCVTAS (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 11 011 FCVTAU (scalar SIMD&FP) Half-precision to 64-bit 1 0 11 11 100 SCVTF (scalar SIMD&FP) 64-bit to half-precision 1 0 11 11 101 UCVTF (scalar SIMD&FP) 64-bit to half-precision 0 1 0 0 1 1 1 0 1 0 1 0 0 1 0 Decode fields Instruction page Encoding size opcode 00 000xx UNALLOCATED 00 00100 AESE 00 00101 AESD 00 00110 AESMC 00 00111 AESIMC 00 01xxx UNALLOCATED 00 1xxxx UNALLOCATED != 00 UNALLOCATED 1 1 0 0 1 1 1 0 0 0 Decode fields Instruction page Encoding Op0 00 EOR3 01 BCAX 10 SM3SS1 11 UNALLOCATED 0 1 0 1 1 1 1 0 0 0 0 0 Decode fields Instruction page Encoding size opcode 00 000 SHA1C 00 001 SHA1P 00 010 SHA1M 00 011 SHA1SU0 00 100 SHA256H 00 101 SHA256H2 00 110 SHA256SU1 00 111 UNALLOCATED != 00 UNALLOCATED 1 1 0 0 1 1 1 0 0 1 1 1 0 0 Decode fields Instruction page Encoding O opcode 0 00 SHA512H 0 01 SHA512H2 0 10 SHA512SU1 0 11 RAX1 1 00 SM3PARTW1 1 01 SM3PARTW2 1 10 SM4EKEY 1 11 UNALLOCATED 1 1 0 0 1 1 1 0 0 1 0 1 0 Decode fields Instruction page Encoding opcode 00 SM3TT1A 01 SM3TT1B 10 SM3TT2A 11 SM3TT2B 1 1 0 0 1 1 1 0 1 0 0 Instruction page Encoding XAR 0 1 0 1 1 1 1 0 1 0 1 0 0 1 0 Decode fields Instruction page Encoding size opcode 00 00000 SHA1H 00 00001 SHA1SU1 00 00010 SHA256SU0 00 00011 UNALLOCATED 00 001xx UNALLOCATED 00 01xxx UNALLOCATED 00 1xxxx UNALLOCATED != 00 UNALLOCATED 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 Decode fields Instruction page Encoding opcode 00 SHA512SU0 01 SM4E 1x UNALLOCATED 0 1 1 1 1 0 1 1 0 0 0 Decode fields Instruction page Encoding M S ftype op opcode2 0 0 00 xx001 UNALLOCATED 0 0 00 xx01x UNALLOCATED 0 0 00 xx1xx UNALLOCATED 0 0 != 00 UNALLOCATED 0 0 00 00 00000 FCMP Single-precision 0 0 00 00 01000 FCMP Single-precision, zero 0 0 00 00 10000 FCMPE Single-precision 0 0 00 00 11000 FCMPE Single-precision, zero 0 0 01 00 00000 FCMP Double-precision 0 0 01 00 01000 FCMP Double-precision, zero 0 0 01 00 10000 FCMPE Double-precision 0 0 01 00 11000 FCMPE Double-precision, zero 0 0 10 00 xx000 UNALLOCATED 0 0 11 00 00000 FCMP Half-precision 0 0 11 00 01000 FCMP Half-precision, zero 0 0 11 00 10000 FCMPE Half-precision 0 0 11 00 11000 FCMPE Half-precision, zero 0 1 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 0 1 0 1 Decode fields Instruction page Encoding M S ftype op 0 0 00 0 FCCMP Single-precision 0 0 00 1 FCCMPE Single-precision 0 0 01 0 FCCMP Double-precision 0 0 01 1 FCCMPE Double-precision 0 0 10 UNALLOCATED 0 0 11 0 FCCMP Half-precision 0 0 11 1 FCCMPE Half-precision 0 1 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 0 1 1 1 Decode fields Instruction page Encoding M S ftype 0 0 00 FCSEL Single-precision 0 0 01 FCSEL Double-precision 0 0 10 UNALLOCATED 0 0 11 FCSEL Half-precision 0 1 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 0 1 1 0 0 0 0 Decode fields Instruction page Encoding M S ftype opcode 0 0 1xxxxx UNALLOCATED 0 0 0x 0101xx UNALLOCATED 0 0 0x 011xxx UNALLOCATED 0 0 00 000000 FMOV (register) Single-precision 0 0 00 000001 FABS (scalar) Single-precision 0 0 00 000010 FNEG (scalar) Single-precision 0 0 00 000011 FSQRT (scalar) Single-precision 0 0 00 0001x0 UNALLOCATED 0 0 00 000101 FCVT Single-precision to double-precision 0 0 00 000111 FCVT Single-precision to half-precision 0 0 00 001000 FRINTN (scalar) Single-precision 0 0 00 001001 FRINTP (scalar) Single-precision 0 0 00 001010 FRINTM (scalar) Single-precision 0 0 00 001011 FRINTZ (scalar) Single-precision 0 0 00 001100 FRINTA (scalar) Single-precision 0 0 00 001110 FRINTX (scalar) Single-precision 0 0 00 001111 FRINTI (scalar) Single-precision 0 0 00 010000 FRINT32Z (scalar) Single-precision 0 0 00 010001 FRINT32X (scalar) Single-precision 0 0 00 010010 FRINT64Z (scalar) Single-precision 0 0 00 010011 FRINT64X (scalar) Single-precision 0 0 01 000000 FMOV (register) Double-precision 0 0 01 000001 FABS (scalar) Double-precision 0 0 01 000010 FNEG (scalar) Double-precision 0 0 01 000011 FSQRT (scalar) Double-precision 0 0 01 000100 FCVT Double-precision to single-precision 0 0 01 000101 UNALLOCATED 0 0 01 000110 BFCVT 0 0 01 000111 FCVT Double-precision to half-precision 0 0 01 001000 FRINTN (scalar) Double-precision 0 0 01 001001 FRINTP (scalar) Double-precision 0 0 01 001010 FRINTM (scalar) Double-precision 0 0 01 001011 FRINTZ (scalar) Double-precision 0 0 01 001100 FRINTA (scalar) Double-precision 0 0 01 001110 FRINTX (scalar) Double-precision 0 0 01 001111 FRINTI (scalar) Double-precision 0 0 01 010000 FRINT32Z (scalar) Double-precision 0 0 01 010001 FRINT32X (scalar) Double-precision 0 0 01 010010 FRINT64Z (scalar) Double-precision 0 0 01 010011 FRINT64X (scalar) Double-precision 0 0 10 0xxxxx UNALLOCATED 0 0 11 000000 FMOV (register) Half-precision 0 0 11 000001 FABS (scalar) Half-precision 0 0 11 000010 FNEG (scalar) Half-precision 0 0 11 000011 FSQRT (scalar) Half-precision 0 0 11 000100 FCVT Half-precision to single-precision 0 0 11 000101 FCVT Half-precision to double-precision 0 0 11 00011x UNALLOCATED 0 0 11 001000 FRINTN (scalar) Half-precision 0 0 11 001001 FRINTP (scalar) Half-precision 0 0 11 001010 FRINTM (scalar) Half-precision 0 0 11 001011 FRINTZ (scalar) Half-precision 0 0 11 001100 FRINTA (scalar) Half-precision 0 0 11 001110 FRINTX (scalar) Half-precision 0 0 11 001111 FRINTI (scalar) Half-precision 0 0 11 01xxxx UNALLOCATED 0 0 != 10 001101 UNALLOCATED 0 1 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 0 1 1 0 Decode fields Instruction page Encoding M S ftype opcode 0 0 00 0000 FMUL (scalar) Single-precision 0 0 00 0001 FDIV (scalar) Single-precision 0 0 00 0010 FADD (scalar) Single-precision 0 0 00 0011 FSUB (scalar) Single-precision 0 0 00 0100 FMAX (scalar) Single-precision 0 0 00 0101 FMIN (scalar) Single-precision 0 0 00 0110 FMAXNM (scalar) Single-precision 0 0 00 0111 FMINNM (scalar) Single-precision 0 0 00 1000 FNMUL (scalar) Single-precision 0 0 01 0000 FMUL (scalar) Double-precision 0 0 01 0001 FDIV (scalar) Double-precision 0 0 01 0010 FADD (scalar) Double-precision 0 0 01 0011 FSUB (scalar) Double-precision 0 0 01 0100 FMAX (scalar) Double-precision 0 0 01 0101 FMIN (scalar) Double-precision 0 0 01 0110 FMAXNM (scalar) Double-precision 0 0 01 0111 FMINNM (scalar) Double-precision 0 0 01 1000 FNMUL (scalar) Double-precision 0 0 10 UNALLOCATED 0 0 11 0000 FMUL (scalar) Half-precision 0 0 11 0001 FDIV (scalar) Half-precision 0 0 11 0010 FADD (scalar) Half-precision 0 0 11 0011 FSUB (scalar) Half-precision 0 0 11 0100 FMAX (scalar) Half-precision 0 0 11 0101 FMIN (scalar) Half-precision 0 0 11 0110 FMAXNM (scalar) Half-precision 0 0 11 0111 FMINNM (scalar) Half-precision 0 0 11 1000 FNMUL (scalar) Half-precision 0 0 != 10 1001 UNALLOCATED 0 0 != 10 101x UNALLOCATED 0 0 != 10 11xx UNALLOCATED 0 1 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 1 Decode fields Instruction page Encoding M S ftype o1 o0 0 0 00 0 0 FMADD Single-precision 0 0 00 0 1 FMSUB Single-precision 0 0 00 1 0 FNMADD Single-precision 0 0 00 1 1 FNMSUB Single-precision 0 0 01 0 0 FMADD Double-precision 0 0 01 0 1 FMSUB Double-precision 0 0 01 1 0 FNMADD Double-precision 0 0 01 1 1 FNMSUB Double-precision 0 0 10 UNALLOCATED 0 0 11 0 0 FMADD Half-precision 0 0 11 0 1 FMSUB Half-precision 0 0 11 1 0 FNMADD Half-precision 0 0 11 1 1 FNMSUB Half-precision 0 1 UNALLOCATED 1 UNALLOCATED 0 1 1 1 1 0 1 1 0 0 Decode fields Instruction page Encoding M S ftype imm5 0 0 != 00000 UNALLOCATED 0 0 00 00000 FMOV (scalar, immediate) Single-precision 0 0 01 00000 FMOV (scalar, immediate) Double-precision 0 0 10 00000 UNALLOCATED 0 0 11 00000 FMOV (scalar, immediate) Half-precision 0 1 UNALLOCATED 1 UNALLOCATED Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Instruction page Encoding UDF SME encodings 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 Decode fields Instruction page Encoding op V opc2 0 1xx UNALLOCATED 0 0 0xx ADDHA 32-bit 0 1 0xx ADDVA 32-bit 1 0 ADDHA 64-bit 1 1 ADDVA 64-bit 1 0 0 0 0 0 0 0 1 0 0 0 0 Decode fields Instruction page Encoding S 0 FMOPA (non-widening) Single-precision 1 FMOPS (non-widening) Single-precision 1 0 0 0 0 0 0 1 1 0 0 0 0 Decode fields Instruction page Encoding S 0 BFMOPA (widening) 1 BFMOPS (widening) 1 0 0 0 0 0 0 1 1 0 1 0 0 Decode fields Instruction page Encoding S 0 FMOPA (widening, 2-way, FP16 to FP32) 1 FMOPS (widening) 1 0 0 0 0 0 0 0 1 0 1 0 0 0 Instruction page Encoding FMOPA (widening, 4-way) 1 0 1 0 0 0 0 1 0 0 0 Decode fields Instruction page Encoding u0 u1 S 0 0 0 SMOPA (4-way) 32-bit 0 0 1 SMOPS (4-way) 32-bit 0 1 0 SUMOPA (4-way) 32-bit 0 1 1 SUMOPS 32-bit 1 0 0 USMOPA (4-way) 32-bit 1 0 1 USMOPS 32-bit 1 1 0 UMOPA (4-way) 32-bit 1 1 1 UMOPS (4-way) 32-bit 1 0 1 0 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding u0 S 0 0 SMOPA (2-way) 0 1 SMOPS (2-way) 1 0 UMOPA (2-way) 1 1 UMOPS (2-way) 1 1 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding msz 00 LD1B (scalar plus scalar, tile slice) 01 LD1H (scalar plus scalar, tile slice) 10 LD1W (scalar plus scalar, tile slice) 11 LD1D (scalar plus scalar, tile slice) 1 1 1 0 0 0 0 0 1 0 Decode fields Instruction page Encoding msz 00 ST1B (scalar plus scalar, tile slice) 01 ST1H (scalar plus scalar, tile slice) 10 ST1W (scalar plus scalar, tile slice) 11 ST1D (scalar plus scalar, tile slice) 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding op 0 LDR (array vector) 1 STR (array vector) 1 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding opc opc2 x0xxxx UNALLOCATED x10xxx UNALLOCATED x110xx UNALLOCATED x1110x UNALLOCATED x11110 UNALLOCATED x11111 != 00 UNALLOCATED 011111 00 LDR (table) 111111 00 STR (table) 1 1 1 0 0 0 0 1 1 1 0 0 Instruction page Encoding LD1Q 1 1 1 0 0 0 0 1 1 1 1 0 Instruction page Encoding ST1Q 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Decode fields Instruction page Encoding size Q 00 0 MOVA (tile to vector, single) 8-bit 01 0 MOVA (tile to vector, single) 16-bit 10 0 MOVA (tile to vector, single) 32-bit 11 0 MOVA (tile to vector, single) 64-bit 11 1 MOVA (tile to vector, single) 128-bit != 11 1 UNALLOCATED 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size 00 MOVA (tile to vector, two registers) 8-bit 01 MOVA (tile to vector, two registers) 16-bit 10 MOVA (tile to vector, two registers) 32-bit 11 MOVA (tile to vector, two registers) 64-bit 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 Decode fields Instruction page Encoding size opc 00 0xx MOVA (tile to vector, four registers) 8-bit 01 0xx MOVA (tile to vector, four registers) 16-bit 10 0xx MOVA (tile to vector, four registers) 32-bit 11 MOVA (tile to vector, four registers) 64-bit != 11 1xx UNALLOCATED 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 Instruction page Encoding MOVA (array to vector, two registers) 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 Instruction page Encoding MOVA (array to vector, four registers) 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Decode fields Instruction page Encoding size Q 00 0 MOVAZ (tile to vector, single) 8-bit 01 0 MOVAZ (tile to vector, single) 16-bit 10 0 MOVAZ (tile to vector, single) 32-bit 11 0 MOVAZ (tile to vector, single) 64-bit 11 1 MOVAZ (tile to vector, single) 128-bit != 11 1 UNALLOCATED 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 Decode fields Instruction page Encoding size 00 MOVAZ (tile to vector, two registers) 8-bit 01 MOVAZ (tile to vector, two registers) 16-bit 10 MOVAZ (tile to vector, two registers) 32-bit 11 MOVAZ (tile to vector, two registers) 64-bit 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 Decode fields Instruction page Encoding size opc 00 0xx MOVAZ (tile to vector, four registers) 8-bit 01 0xx MOVAZ (tile to vector, four registers) 16-bit 10 0xx MOVAZ (tile to vector, four registers) 32-bit 11 MOVAZ (tile to vector, four registers) 64-bit != 11 1xx UNALLOCATED 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 Instruction page Encoding MOVAZ (array to vector, two registers) 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 Instruction page Encoding MOVAZ (array to vector, four registers) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size Q 00 0 MOVA (vector to tile, single) 8-bit 01 0 MOVA (vector to tile, single) 16-bit 10 0 MOVA (vector to tile, single) 32-bit 11 0 MOVA (vector to tile, single) 64-bit 11 1 MOVA (vector to tile, single) 128-bit != 11 1 UNALLOCATED 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size 00 MOVA (vector to tile, two registers) 8-bit 01 MOVA (vector to tile, two registers) 16-bit 10 MOVA (vector to tile, two registers) 32-bit 11 MOVA (vector to tile, two registers) 64-bit 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Decode fields Instruction page Encoding size opc 00 0xx MOVA (vector to tile, four registers) 8-bit 01 0xx MOVA (vector to tile, four registers) 16-bit 10 0xx MOVA (vector to tile, four registers) 32-bit 11 MOVA (vector to tile, four registers) 64-bit != 11 1xx UNALLOCATED 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Instruction page Encoding MOVA (vector to array, two registers) 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 Instruction page Encoding MOVA (vector to array, four registers) 1 0 0 0 0 0 0 0 1 1 0 0 Decode fields Instruction page Encoding S 0 FMOPA (non-widening) Double-precision 1 FMOPS (non-widening) Double-precision 1 0 1 0 0 0 0 1 1 0 Decode fields Instruction page Encoding u0 u1 S 0 0 0 SMOPA (4-way) 64-bit 0 0 1 SMOPS (4-way) 64-bit 0 1 0 SUMOPA (4-way) 64-bit 0 1 1 SUMOPS 64-bit 1 0 0 USMOPA (4-way) 64-bit 1 0 1 USMOPS 64-bit 1 1 0 UMOPA (4-way) 64-bit 1 1 1 UMOPS (4-way) 64-bit 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Instruction page Encoding ZERO (tiles) 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 Decode fields Instruction page Encoding opc opc2 != 00 UNALLOCATED 00xx 00 UNALLOCATED 01xx 00 LUTI4 (two registers) Consecutive 1xxx 00 LUTI2 (two registers) Consecutive 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 Decode fields Instruction page Encoding opc opc2 != 00 UNALLOCATED 00x 00 UNALLOCATED 01x 00 LUTI4 (four registers, 16-bit and 32-bit) Consecutive 1xx 00 LUTI2 (four registers) Consecutive 1 1 0 0 0 0 0 0 1 1 0 0 1 Decode fields Instruction page Encoding opc opc2 != 00 UNALLOCATED 00xxx 00 UNALLOCATED 01xxx 00 LUTI4 (single) 1xxxx 00 LUTI2 (single) 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 Decode fields Instruction page Encoding opc 00 LUTI4 (four registers, 8-bit) Consecutive != 00 UNALLOCATED 1 1 0 0 0 0 0 0 1 0 0 1 1 1 0 Decode fields Instruction page Encoding opc opc2 != 00 UNALLOCATED 00xx 00 UNALLOCATED 01xx 00 LUTI4 (two registers) Strided 1xxx 00 LUTI2 (two registers) Strided 1 1 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 Decode fields Instruction page Encoding opc opc2 != 00 UNALLOCATED 00x 00 UNALLOCATED 01x 00 LUTI4 (four registers, 16-bit and 32-bit) Strided 1xx 00 LUTI2 (four registers) Strided 1 1 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 Decode fields Instruction page Encoding opc 00 LUTI4 (four registers, 8-bit) Strided != 00 UNALLOCATED 1 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 Decode fields Instruction page Encoding opc 0011111 MOVT (table to scalar) != 0011111 UNALLOCATED 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 Decode fields Instruction page Encoding opc 0011111 MOVT (scalar to table) != 0011111 UNALLOCATED 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 Decode fields Instruction page Encoding opc 0011111 MOVT (vector to table) != 0011111 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 Decode fields Instruction page Encoding size 00 BFMUL (multiple vectors) Two registers != 00 FMUL (multiple vectors) Two registers 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding size 00 BFMUL (multiple vectors) Four registers != 00 FMUL (multiple vectors) Four registers 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 Decode fields Instruction page Encoding op U S 0 0 0 SMLALL (multiple and indexed vector) Four ZA quad-vectors of 32-bit elements 0 0 1 SMLSLL (multiple and indexed vector) Four ZA quad-vectors of 32-bit elements 0 1 0 UMLALL (multiple and indexed vector) Four ZA quad-vectors of 32-bit elements 0 1 1 UMLSLL (multiple and indexed vector) Four ZA quad-vectors of 32-bit elements 1 1 UNALLOCATED 1 0 0 USMLALL (multiple and indexed vector) Four ZA quad-vectors 1 1 0 SUMLALL (multiple and indexed vector) Four ZA quad-vectors 1 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 Instruction page Encoding FMLALL (multiple and indexed vector) Four ZA quad-vectors 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 Decode fields Instruction page Encoding op S 0 0 FMLA (multiple and indexed vector) Four ZA single-vectors of half-precision elements 0 1 FMLS (multiple and indexed vector) Four ZA single-vectors of half-precision elements 1 0 BFMLA (multiple and indexed vector) Four ZA single-vectors 1 1 BFMLS (multiple and indexed vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 Instruction page Encoding FDOT (2-way, multiple and indexed vector, FP8 to FP16) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 1 1 0 Decode fields Instruction page Encoding op opc2 0 000 FMLA (multiple and indexed vector) Four ZA single-vectors of single-precision elements 0 001 FDOT (4-way, multiple and indexed vector) Four ZA single-vectors 0 010 FMLS (multiple and indexed vector) Four ZA single-vectors of single-precision elements 0 011 UNALLOCATED 0 100 SVDOT (4-way) 8-bit to 32-bit 0 101 USVDOT 0 110 UVDOT (4-way) 8-bit to 32-bit 0 111 SUVDOT 1 000 SDOT (2-way, multiple and indexed vector) Four ZA single-vectors 1 001 FDOT (2-way, multiple and indexed vector, FP16 to FP32) Four ZA single-vectors 1 010 UDOT (2-way, multiple and indexed vector) Four ZA single-vectors 1 011 BFDOT (multiple and indexed vector) Four ZA single-vectors 1 100 SDOT (4-way, multiple and indexed vector) Four ZA single-vectors of 32-bit elements 1 101 USDOT (4-way, multiple and indexed vector) Four ZA single-vectors 1 110 UDOT (4-way, multiple and indexed vector) Four ZA single-vectors of 32-bit elements 1 111 SUDOT (4-way, multiple and indexed vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 Decode fields Instruction page Encoding U S 0 0 SMLALL (multiple and indexed vector) Four ZA quad-vectors of 64-bit elements 0 1 SMLSLL (multiple and indexed vector) Four ZA quad-vectors of 64-bit elements 1 0 UMLALL (multiple and indexed vector) Four ZA quad-vectors of 64-bit elements 1 1 UMLSLL (multiple and indexed vector) Four ZA quad-vectors of 64-bit elements 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 Decode fields Instruction page Encoding op S 0 0 FMLAL (multiple and indexed vector, FP16 to FP32) Four ZA double-vectors 0 1 FMLSL (multiple and indexed vector) Four ZA double-vectors 1 0 BFMLAL (multiple and indexed vector) Four ZA double-vectors 1 1 BFMLSL (multiple and indexed vector) Four ZA double-vectors 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 1 0 Instruction page Encoding FMLAL (multiple and indexed vector, FP8 to FP16) Four ZA double-vectors 1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 0 Decode fields Instruction page Encoding op opc2 0 00 FMLA (multiple and indexed vector) Four ZA single-vectors of double-precision elements 0 01 SDOT (4-way, multiple and indexed vector) Four ZA single-vectors of 64-bit elements 0 10 FMLS (multiple and indexed vector) Four ZA single-vectors of double-precision elements 0 11 UDOT (4-way, multiple and indexed vector) Four ZA single-vectors of 64-bit elements 1 x0 UNALLOCATED 1 01 SVDOT (4-way) 16-bit to 64-bit 1 11 UVDOT (4-way) 16-bit to 64-bit 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 0 Decode fields Instruction page Encoding U S 0 0 SMLAL (multiple and indexed vector) Four ZA double-vectors 0 1 SMLSL (multiple and indexed vector) Four ZA double-vectors 1 0 UMLAL (multiple and indexed vector) Four ZA double-vectors 1 1 UMLSL (multiple and indexed vector) Four ZA double-vectors 1 1 0 0 0 0 0 1 0 0 0 0 Decode fields Instruction page Encoding U S op 1 1 UNALLOCATED 0 0 0 SMLALL (multiple and indexed vector) One ZA quad-vector of 32-bit elements 0 0 1 USMLALL (multiple and indexed vector) One ZA quad-vector 0 1 0 SMLSLL (multiple and indexed vector) One ZA quad-vector of 32-bit elements 1 0 0 UMLALL (multiple and indexed vector) One ZA quad-vector of 32-bit elements 1 0 1 SUMLALL (multiple and indexed vector) One ZA quad-vector 1 1 0 UMLSLL (multiple and indexed vector) One ZA quad-vector of 32-bit elements 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 Instruction page Encoding FMLALL (multiple and indexed vector) One ZA quad-vector 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Decode fields Instruction page Encoding U S 0 0 SMLALL (multiple and indexed vector) One ZA quad-vector of 64-bit elements 0 1 SMLSLL (multiple and indexed vector) One ZA quad-vector of 64-bit elements 1 0 UMLALL (multiple and indexed vector) One ZA quad-vector of 64-bit elements 1 1 UMLSLL (multiple and indexed vector) One ZA quad-vector of 64-bit elements 1 1 0 0 0 0 0 1 1 0 0 0 1 Decode fields Instruction page Encoding op S 0 0 FMLAL (multiple and indexed vector, FP16 to FP32) One ZA double-vector 0 1 FMLSL (multiple and indexed vector) One ZA double-vector 1 0 BFMLAL (multiple and indexed vector) One ZA double-vector 1 1 BFMLSL (multiple and indexed vector) One ZA double-vector 1 1 0 0 0 0 0 1 1 1 0 0 0 0 Instruction page Encoding FMLAL (multiple and indexed vector, FP8 to FP16) One ZA double-vector 1 1 0 0 0 0 0 1 1 1 0 0 1 Decode fields Instruction page Encoding U S 0 0 SMLAL (multiple and indexed vector) One ZA double-vector 0 1 SMLSL (multiple and indexed vector) One ZA double-vector 1 0 UMLAL (multiple and indexed vector) One ZA double-vector 1 1 UMLSL (multiple and indexed vector) One ZA double-vector 1 1 0 0 0 0 0 1 0 0 0 1 0 0 Decode fields Instruction page Encoding op U S 0 0 0 SMLALL (multiple and indexed vector) Two ZA quad-vectors of 32-bit elements 0 0 1 SMLSLL (multiple and indexed vector) Two ZA quad-vectors of 32-bit elements 0 1 0 UMLALL (multiple and indexed vector) Two ZA quad-vectors of 32-bit elements 0 1 1 UMLSLL (multiple and indexed vector) Two ZA quad-vectors of 32-bit elements 1 1 UNALLOCATED 1 0 0 USMLALL (multiple and indexed vector) Two ZA quad-vectors 1 1 0 SUMLALL (multiple and indexed vector) Two ZA quad-vectors 1 1 0 0 0 0 0 1 0 0 0 1 0 1 Decode fields Instruction page Encoding op S 0 0 FMLA (multiple and indexed vector) Two ZA single-vectors of half-precision elements 0 1 FMLS (multiple and indexed vector) Two ZA single-vectors of half-precision elements 1 0 BFMLA (multiple and indexed vector) Two ZA single-vectors 1 1 BFMLS (multiple and indexed vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 1 0 Decode fields Instruction page Encoding op opc2 0 000 FMLA (multiple and indexed vector) Two ZA single-vectors of single-precision elements 0 001 FVDOT (FP16 to FP32) 0 010 FMLS (multiple and indexed vector) Two ZA single-vectors of single-precision elements 0 011 BFVDOT 0 100 SVDOT (2-way) 0 101 UNALLOCATED 0 110 UVDOT (2-way) 0 111 FDOT (4-way, multiple and indexed vector) Two ZA single-vectors 1 000 SDOT (2-way, multiple and indexed vector) Two ZA single-vectors 1 001 FDOT (2-way, multiple and indexed vector, FP16 to FP32) Two ZA single-vectors 1 010 UDOT (2-way, multiple and indexed vector) Two ZA single-vectors 1 011 BFDOT (multiple and indexed vector) Two ZA single-vectors 1 100 SDOT (4-way, multiple and indexed vector) Two ZA single-vectors of 32-bit elements 1 101 USDOT (4-way, multiple and indexed vector) Two ZA single-vectors 1 110 UDOT (4-way, multiple and indexed vector) Two ZA single-vectors of 32-bit elements 1 111 SUDOT (4-way, multiple and indexed vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding U S 0 0 SMLALL (multiple and indexed vector) Two ZA quad-vectors of 64-bit elements 0 1 SMLSLL (multiple and indexed vector) Two ZA quad-vectors of 64-bit elements 1 0 UMLALL (multiple and indexed vector) Two ZA quad-vectors of 64-bit elements 1 1 UMLSLL (multiple and indexed vector) Two ZA quad-vectors of 64-bit elements 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 Instruction page Encoding FMLALL (multiple and indexed vector) Two ZA quad-vectors 1 1 0 0 0 0 0 1 1 0 0 1 0 1 0 Decode fields Instruction page Encoding op S 0 0 FMLAL (multiple and indexed vector, FP16 to FP32) Two ZA double-vectors 0 1 FMLSL (multiple and indexed vector) Two ZA double-vectors 1 0 BFMLAL (multiple and indexed vector) Two ZA double-vectors 1 1 BFMLSL (multiple and indexed vector) Two ZA double-vectors 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 Instruction page Encoding FMLAL (multiple and indexed vector, FP8 to FP16) Two ZA double-vectors 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 0 Decode fields Instruction page Encoding T 0 FVDOTB 1 FVDOTT 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 0 Decode fields Instruction page Encoding opc 00 FMLA (multiple and indexed vector) Two ZA single-vectors of double-precision elements 01 SDOT (4-way, multiple and indexed vector) Two ZA single-vectors of 64-bit elements 10 FMLS (multiple and indexed vector) Two ZA single-vectors of double-precision elements 11 UDOT (4-way, multiple and indexed vector) Two ZA single-vectors of 64-bit elements 1 1 0 0 0 0 0 1 1 1 0 1 0 1 0 Decode fields Instruction page Encoding U S 0 0 SMLAL (multiple and indexed vector) Two ZA double-vectors 0 1 SMLSL (multiple and indexed vector) Two ZA double-vectors 1 0 UMLAL (multiple and indexed vector) Two ZA double-vectors 1 1 UMLSL (multiple and indexed vector) Two ZA double-vectors 1 1 0 0 0 0 0 1 1 1 0 1 0 1 0 Decode fields Instruction page Encoding op 0 FDOT (2-way, multiple and indexed vector, FP8 to FP16) Two ZA single-vectors 1 FVDOT (FP8 to FP16) 1 0 1 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus scalar, consecutive registers) Two registers 00 1 LDNT1B (scalar plus scalar, consecutive registers) Two registers 01 0 LD1H (scalar plus scalar, consecutive registers) Two registers 01 1 LDNT1H (scalar plus scalar, consecutive registers) Two registers 10 0 LD1W (scalar plus scalar, consecutive registers) Two registers 10 1 LDNT1W (scalar plus scalar, consecutive registers) Two registers 11 0 LD1D (scalar plus scalar, consecutive registers) Two registers 11 1 LDNT1D (scalar plus scalar, consecutive registers) Two registers 1 0 1 0 0 0 0 0 0 0 0 1 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus scalar, consecutive registers) Four registers 00 1 LDNT1B (scalar plus scalar, consecutive registers) Four registers 01 0 LD1H (scalar plus scalar, consecutive registers) Four registers 01 1 LDNT1H (scalar plus scalar, consecutive registers) Four registers 10 0 LD1W (scalar plus scalar, consecutive registers) Four registers 10 1 LDNT1W (scalar plus scalar, consecutive registers) Four registers 11 0 LD1D (scalar plus scalar, consecutive registers) Four registers 11 1 LDNT1D (scalar plus scalar, consecutive registers) Four registers 1 0 1 0 0 0 0 0 0 0 1 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus scalar, consecutive registers) Two registers 00 1 STNT1B (scalar plus scalar, consecutive registers) Two registers 01 0 ST1H (scalar plus scalar, consecutive registers) Two registers 01 1 STNT1H (scalar plus scalar, consecutive registers) Two registers 10 0 ST1W (scalar plus scalar, consecutive registers) Two registers 10 1 STNT1W (scalar plus scalar, consecutive registers) Two registers 11 0 ST1D (scalar plus scalar, consecutive registers) Two registers 11 1 STNT1D (scalar plus scalar, consecutive registers) Two registers 1 0 1 0 0 0 0 0 0 0 1 1 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus scalar, consecutive registers) Four registers 00 1 STNT1B (scalar plus scalar, consecutive registers) Four registers 01 0 ST1H (scalar plus scalar, consecutive registers) Four registers 01 1 STNT1H (scalar plus scalar, consecutive registers) Four registers 10 0 ST1W (scalar plus scalar, consecutive registers) Four registers 10 1 STNT1W (scalar plus scalar, consecutive registers) Four registers 11 0 ST1D (scalar plus scalar, consecutive registers) Four registers 11 1 STNT1D (scalar plus scalar, consecutive registers) Four registers 1 0 1 0 0 0 0 0 0 1 0 0 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus immediate, consecutive registers) Two registers 00 1 LDNT1B (scalar plus immediate, consecutive registers) Two registers 01 0 LD1H (scalar plus immediate, consecutive registers) Two registers 01 1 LDNT1H (scalar plus immediate, consecutive registers) Two registers 10 0 LD1W (scalar plus immediate, consecutive registers) Two registers 10 1 LDNT1W (scalar plus immediate, consecutive registers) Two registers 11 0 LD1D (scalar plus immediate, consecutive registers) Two registers 11 1 LDNT1D (scalar plus immediate, consecutive registers) Two registers 1 0 1 0 0 0 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus immediate, consecutive registers) Four registers 00 1 LDNT1B (scalar plus immediate, consecutive registers) Four registers 01 0 LD1H (scalar plus immediate, consecutive registers) Four registers 01 1 LDNT1H (scalar plus immediate, consecutive registers) Four registers 10 0 LD1W (scalar plus immediate, consecutive registers) Four registers 10 1 LDNT1W (scalar plus immediate, consecutive registers) Four registers 11 0 LD1D (scalar plus immediate, consecutive registers) Four registers 11 1 LDNT1D (scalar plus immediate, consecutive registers) Four registers 1 0 1 0 0 0 0 0 0 1 1 0 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus immediate, consecutive registers) Two registers 00 1 STNT1B (scalar plus immediate, consecutive registers) Two registers 01 0 ST1H (scalar plus immediate, consecutive registers) Two registers 01 1 STNT1H (scalar plus immediate, consecutive registers) Two registers 10 0 ST1W (scalar plus immediate, consecutive registers) Two registers 10 1 STNT1W (scalar plus immediate, consecutive registers) Two registers 11 0 ST1D (scalar plus immediate, consecutive registers) Two registers 11 1 STNT1D (scalar plus immediate, consecutive registers) Two registers 1 0 1 0 0 0 0 0 0 1 1 0 1 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus immediate, consecutive registers) Four registers 00 1 STNT1B (scalar plus immediate, consecutive registers) Four registers 01 0 ST1H (scalar plus immediate, consecutive registers) Four registers 01 1 STNT1H (scalar plus immediate, consecutive registers) Four registers 10 0 ST1W (scalar plus immediate, consecutive registers) Four registers 10 1 STNT1W (scalar plus immediate, consecutive registers) Four registers 11 0 ST1D (scalar plus immediate, consecutive registers) Four registers 11 1 STNT1D (scalar plus immediate, consecutive registers) Four registers 1 0 1 0 0 0 0 1 0 0 0 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus scalar, strided registers) Two registers 00 1 LDNT1B (scalar plus scalar, strided registers) Two registers 01 0 LD1H (scalar plus scalar, strided registers) Two registers 01 1 LDNT1H (scalar plus scalar, strided registers) Two registers 10 0 LD1W (scalar plus scalar, strided registers) Two registers 10 1 LDNT1W (scalar plus scalar, strided registers) Two registers 11 0 LD1D (scalar plus scalar, strided registers) Two registers 11 1 LDNT1D (scalar plus scalar, strided registers) Two registers 1 0 1 0 0 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus scalar, strided registers) Four registers 00 1 LDNT1B (scalar plus scalar, strided registers) Four registers 01 0 LD1H (scalar plus scalar, strided registers) Four registers 01 1 LDNT1H (scalar plus scalar, strided registers) Four registers 10 0 LD1W (scalar plus scalar, strided registers) Four registers 10 1 LDNT1W (scalar plus scalar, strided registers) Four registers 11 0 LD1D (scalar plus scalar, strided registers) Four registers 11 1 LDNT1D (scalar plus scalar, strided registers) Four registers 1 0 1 0 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus scalar, strided registers) Two registers 00 1 STNT1B (scalar plus scalar, strided registers) Two registers 01 0 ST1H (scalar plus scalar, strided registers) Two registers 01 1 STNT1H (scalar plus scalar, strided registers) Two registers 10 0 ST1W (scalar plus scalar, strided registers) Two registers 10 1 STNT1W (scalar plus scalar, strided registers) Two registers 11 0 ST1D (scalar plus scalar, strided registers) Two registers 11 1 STNT1D (scalar plus scalar, strided registers) Two registers 1 0 1 0 0 0 0 1 0 0 1 1 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus scalar, strided registers) Four registers 00 1 STNT1B (scalar plus scalar, strided registers) Four registers 01 0 ST1H (scalar plus scalar, strided registers) Four registers 01 1 STNT1H (scalar plus scalar, strided registers) Four registers 10 0 ST1W (scalar plus scalar, strided registers) Four registers 10 1 STNT1W (scalar plus scalar, strided registers) Four registers 11 0 ST1D (scalar plus scalar, strided registers) Four registers 11 1 STNT1D (scalar plus scalar, strided registers) Four registers 1 0 1 0 0 0 0 1 0 1 0 0 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus immediate, strided registers) Two registers 00 1 LDNT1B (scalar plus immediate, strided registers) Two registers 01 0 LD1H (scalar plus immediate, strided registers) Two registers 01 1 LDNT1H (scalar plus immediate, strided registers) Two registers 10 0 LD1W (scalar plus immediate, strided registers) Two registers 10 1 LDNT1W (scalar plus immediate, strided registers) Two registers 11 0 LD1D (scalar plus immediate, strided registers) Two registers 11 1 LDNT1D (scalar plus immediate, strided registers) Two registers 1 0 1 0 0 0 0 1 0 1 0 0 1 0 Decode fields Instruction page Encoding msz N 00 0 LD1B (scalar plus immediate, strided registers) Four registers 00 1 LDNT1B (scalar plus immediate, strided registers) Four registers 01 0 LD1H (scalar plus immediate, strided registers) Four registers 01 1 LDNT1H (scalar plus immediate, strided registers) Four registers 10 0 LD1W (scalar plus immediate, strided registers) Four registers 10 1 LDNT1W (scalar plus immediate, strided registers) Four registers 11 0 LD1D (scalar plus immediate, strided registers) Four registers 11 1 LDNT1D (scalar plus immediate, strided registers) Four registers 1 0 1 0 0 0 0 1 0 1 1 0 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus immediate, strided registers) Two registers 00 1 STNT1B (scalar plus immediate, strided registers) Two registers 01 0 ST1H (scalar plus immediate, strided registers) Two registers 01 1 STNT1H (scalar plus immediate, strided registers) Two registers 10 0 ST1W (scalar plus immediate, strided registers) Two registers 10 1 STNT1W (scalar plus immediate, strided registers) Two registers 11 0 ST1D (scalar plus immediate, strided registers) Two registers 11 1 STNT1D (scalar plus immediate, strided registers) Two registers 1 0 1 0 0 0 0 1 0 1 1 0 1 0 Decode fields Instruction page Encoding msz N 00 0 ST1B (scalar plus immediate, strided registers) Four registers 00 1 STNT1B (scalar plus immediate, strided registers) Four registers 01 0 ST1H (scalar plus immediate, strided registers) Four registers 01 1 STNT1H (scalar plus immediate, strided registers) Four registers 10 0 ST1W (scalar plus immediate, strided registers) Four registers 10 1 STNT1W (scalar plus immediate, strided registers) Four registers 11 0 ST1D (scalar plus immediate, strided registers) Four registers 11 1 STNT1D (scalar plus immediate, strided registers) Four registers 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding sz U S op 0 0 0 SMLALL (multiple vectors) Four ZA quad-vectors 0 1 0 SMLSLL (multiple vectors) Four ZA quad-vectors 1 0 0 UMLALL (multiple vectors) Four ZA quad-vectors 1 1 0 UMLSLL (multiple vectors) Four ZA quad-vectors 0 0 0 1 USMLALL (multiple vectors) Four ZA quad-vectors 0 0 1 1 UNALLOCATED 0 1 1 UNALLOCATED 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 Instruction page Encoding FMLALL (multiple vectors) Four ZA quad-vectors 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding op S 0 0 FMLAL (multiple vectors, FP16 to FP32) Four ZA double-vectors 0 1 FMLSL (multiple vectors) Four ZA double-vectors 1 0 BFMLAL (multiple vectors) Four ZA double-vectors 1 1 BFMLSL (multiple vectors) Four ZA double-vectors 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 0 Instruction page Encoding FMLAL (multiple vectors, FP8 to FP16) Four ZA double-vectors 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding U S 0 0 SMLAL (multiple vectors) Four ZA double-vectors 0 1 SMLSL (multiple vectors) Four ZA double-vectors 1 0 UMLAL (multiple vectors) Four ZA double-vectors 1 1 UMLSL (multiple vectors) Four ZA double-vectors 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 Decode fields Instruction page Encoding opc 00 FDOT (2-way, multiple vectors, FP16 to FP32) Four ZA single-vectors 01 BFDOT (multiple vectors) Four ZA single-vectors 10 FDOT (2-way, multiple vectors, FP8 to FP16) Four ZA single-vectors 11 FDOT (4-way, multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 1 Decode fields Instruction page Encoding sz S 0 0 FMLA (multiple vectors) Four ZA single-vectors of half-precision elements 0 1 FMLS (multiple vectors) Four ZA single-vectors of half-precision elements 1 0 BFMLA (multiple vectors) Four ZA single-vectors 1 1 BFMLS (multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 Decode fields Instruction page Encoding U 0 SDOT (4-way, multiple vectors) Four ZA single-vectors 1 UDOT (4-way, multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 Instruction page Encoding USDOT (4-way, multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 Decode fields Instruction page Encoding U 0 SDOT (2-way, multiple vectors) Four ZA single-vectors 1 UDOT (2-way, multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 Decode fields Instruction page Encoding S 0 FMLA (multiple vectors) Four ZA single-vectors 1 FMLS (multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 0 0 0 1 Decode fields Instruction page Encoding S 0 ADD (to array, multiple vectors) Four ZA single-vectors 1 SUB (to array, multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 Decode fields Instruction page Encoding S 0 FADD Four ZA single-vectors 1 FSUB Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 1 Decode fields Instruction page Encoding S 0 ADD (to array, array and multiple vectors) Four ZA single-vectors 1 SUB (to array, array and multiple vectors) Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 0 Decode fields Instruction page Encoding sz S 0 0 FADD Four ZA single-vectors of half-precision elements 0 1 FSUB Four ZA single-vectors of half-precision elements 1 0 BFADD Four ZA single-vectors 1 1 BFSUB Four ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding sz U S op 0 0 0 SMLALL (multiple vectors) Two ZA quad-vectors 0 1 0 SMLSLL (multiple vectors) Two ZA quad-vectors 1 0 0 UMLALL (multiple vectors) Two ZA quad-vectors 1 1 0 UMLSLL (multiple vectors) Two ZA quad-vectors 0 0 0 1 USMLALL (multiple vectors) Two ZA quad-vectors 0 0 1 1 UNALLOCATED 0 1 1 UNALLOCATED 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 Instruction page Encoding FMLALL (multiple vectors) Two ZA quad-vectors 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 Decode fields Instruction page Encoding op S 0 0 FMLAL (multiple vectors, FP16 to FP32) Two ZA double-vectors 0 1 FMLSL (multiple vectors) Two ZA double-vectors 1 0 BFMLAL (multiple vectors) Two ZA double-vectors 1 1 BFMLSL (multiple vectors) Two ZA double-vectors 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 Instruction page Encoding FMLAL (multiple vectors, FP8 to FP16) Two ZA double-vectors 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 Decode fields Instruction page Encoding U S 0 0 SMLAL (multiple vectors) Two ZA double-vectors 0 1 SMLSL (multiple vectors) Two ZA double-vectors 1 0 UMLAL (multiple vectors) Two ZA double-vectors 1 1 UMLSL (multiple vectors) Two ZA double-vectors 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 Decode fields Instruction page Encoding opc 00 FDOT (2-way, multiple vectors, FP16 to FP32) Two ZA single-vectors 01 BFDOT (multiple vectors) Two ZA single-vectors 10 FDOT (2-way, multiple vectors, FP8 to FP16) Two ZA single-vectors 11 FDOT (4-way, multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 Decode fields Instruction page Encoding sz S 0 0 FMLA (multiple vectors) Two ZA single-vectors of half-precision elements 0 1 FMLS (multiple vectors) Two ZA single-vectors of half-precision elements 1 0 BFMLA (multiple vectors) Two ZA single-vectors 1 1 BFMLS (multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 Decode fields Instruction page Encoding U 0 SDOT (4-way, multiple vectors) Two ZA single-vectors 1 UDOT (4-way, multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 Instruction page Encoding USDOT (4-way, multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 Decode fields Instruction page Encoding U 0 SDOT (2-way, multiple vectors) Two ZA single-vectors 1 UDOT (2-way, multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 Decode fields Instruction page Encoding S 0 FMLA (multiple vectors) Two ZA single-vectors 1 FMLS (multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 Decode fields Instruction page Encoding S 0 ADD (to array, multiple vectors) Two ZA single-vectors 1 SUB (to array, multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 Decode fields Instruction page Encoding S 0 FADD Two ZA single-vectors 1 FSUB Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 Decode fields Instruction page Encoding S 0 ADD (to array, array and multiple vectors) Two ZA single-vectors 1 SUB (to array, array and multiple vectors) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 Decode fields Instruction page Encoding sz S 0 0 FADD Two ZA single-vectors of half-precision elements 0 1 FSUB Two ZA single-vectors of half-precision elements 1 0 BFADD Two ZA single-vectors 1 1 BFSUB Two ZA single-vectors 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 Decode fields Instruction page Encoding opc U 00 0 SMAX (multiple vectors) Four registers 00 1 UMAX (multiple vectors) Four registers 01 0 SMIN (multiple vectors) Four registers 01 1 UMIN (multiple vectors) Four registers 1x UNALLOCATED 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 1 0 0 Decode fields Instruction page Encoding size opc o2 10 0 FAMAX Four registers 10 1 FAMIN Four registers 11 UNALLOCATED 00 00 0 BFMAX (multiple vectors) Four registers 00 00 1 BFMIN (multiple vectors) Four registers 00 01 0 BFMAXNM (multiple vectors) Four registers 00 01 1 BFMINNM (multiple vectors) Four registers != 00 00 0 FMAX (multiple vectors) Four registers != 00 00 1 FMIN (multiple vectors) Four registers != 00 01 0 FMAXNM (multiple vectors) Four registers != 00 01 1 FMINNM (multiple vectors) Four registers 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 1 1 0 Decode fields Instruction page Encoding size opc o2 00 1 UNALLOCATED != 00 UNALLOCATED 00 00 0 BFSCALE (multiple vectors) Four registers != 00 00 0 FSCALE (multiple vectors) Four registers 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1 0 0 Decode fields Instruction page Encoding opc U 001 0 SRSHL (multiple vectors) Four registers 001 1 URSHL (multiple vectors) Four registers != 001 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 Decode fields Instruction page Encoding opc U 00 0 SMAX (multiple vectors) Two registers 00 1 UMAX (multiple vectors) Two registers 01 0 SMIN (multiple vectors) Two registers 01 1 UMIN (multiple vectors) Two registers 1x UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 0 Decode fields Instruction page Encoding size opc o2 10 0 FAMAX Two registers 10 1 FAMIN Two registers 11 UNALLOCATED 00 00 0 BFMAX (multiple vectors) Two registers 00 00 1 BFMIN (multiple vectors) Two registers 00 01 0 BFMAXNM (multiple vectors) Two registers 00 01 1 BFMINNM (multiple vectors) Two registers != 00 00 0 FMAX (multiple vectors) Two registers != 00 00 1 FMIN (multiple vectors) Two registers != 00 01 0 FMAXNM (multiple vectors) Two registers != 00 01 1 FMINNM (multiple vectors) Two registers 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 1 Decode fields Instruction page Encoding size opc o2 00 1 UNALLOCATED != 00 UNALLOCATED 00 00 0 BFSCALE (multiple vectors) Two registers != 00 00 0 FSCALE (multiple vectors) Two registers 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 1 0 Decode fields Instruction page Encoding opc U 001 0 SRSHL (multiple vectors) Two registers 001 1 URSHL (multiple vectors) Two registers != 001 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op 0 SQDMULH (multiple vectors) Four registers 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 0 0 0 Decode fields Instruction page Encoding op 0 SQDMULH (multiple vectors) Two registers 1 UNALLOCATED 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 Decode fields Instruction page Encoding sz U S op 0 0 0 SMLALL (multiple and single vector) Four ZA quad-vectors 0 1 0 SMLSLL (multiple and single vector) Four ZA quad-vectors 1 0 0 UMLALL (multiple and single vector) Four ZA quad-vectors 1 1 0 UMLSLL (multiple and single vector) Four ZA quad-vectors 0 1 1 UNALLOCATED 0 0 0 1 USMLALL (multiple and single vector) Four ZA quad-vectors 0 1 0 1 SUMLALL (multiple and single vector) Four ZA quad-vectors 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 Instruction page Encoding FMLALL (multiple and single vector) Four ZA quad-vectors 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 Instruction page Encoding FMLALL (multiple and single vector) One ZA quad-vector 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 Decode fields Instruction page Encoding op S o2 0 0 0 FMLAL (multiple and single vector, FP16 to FP32) Four ZA double-vectors 0 0 1 FMLAL (multiple and single vector, FP8 to FP16) Four ZA double-vectors 0 1 0 FMLSL (multiple and single vector) Four ZA double-vectors 0 1 1 UNALLOCATED 1 1 UNALLOCATED 1 0 0 BFMLAL (multiple and single vector) Four ZA double-vectors 1 1 0 BFMLSL (multiple and single vector) Four ZA double-vectors 1 1 0 0 0 0 0 1 0 1 1 1 0 0 1 0 Decode fields Instruction page Encoding U S op 1 UNALLOCATED 0 0 0 SMLAL (multiple and single vector) Four ZA double-vectors 0 1 0 SMLSL (multiple and single vector) Four ZA double-vectors 1 0 0 UMLAL (multiple and single vector) Four ZA double-vectors 1 1 0 UMLSL (multiple and single vector) Four ZA double-vectors 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 Instruction page Encoding FMLAL (multiple and single vector, FP8 to FP16) One ZA double-vector 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 0 Decode fields Instruction page Encoding opc 00 FDOT (2-way, multiple and single vector, FP16 to FP32) Four ZA single-vectors 01 FDOT (2-way, multiple and single vector, FP8 to FP16) Four ZA single-vectors 10 BFDOT (multiple and single vector) Four ZA single-vectors 11 FDOT (4-way, multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 0 Decode fields Instruction page Encoding U 0 SDOT (4-way, multiple and single vector) Four ZA single-vectors 1 UDOT (4-way, multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 Decode fields Instruction page Encoding U 0 USDOT (4-way, multiple and single vector) Four ZA single-vectors 1 SUDOT (4-way, multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 1 1 0 1 0 1 1 Decode fields Instruction page Encoding U 0 SDOT (2-way, multiple and single vector) Four ZA single-vectors 1 UDOT (2-way, multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 Decode fields Instruction page Encoding S 0 FMLA (multiple and single vector) Four ZA single-vectors 1 FMLS (multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 1 0 1 1 0 1 Decode fields Instruction page Encoding S 0 ADD (to array, multiple and single vector) Four ZA single-vectors 1 SUB (to array, multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 1 0 1 1 1 0 Decode fields Instruction page Encoding sz S 0 0 FMLA (multiple and single vector) Four ZA single-vectors of half-precision elements 0 1 FMLS (multiple and single vector) Four ZA single-vectors of half-precision elements 1 0 BFMLA (multiple and single vector) Four ZA single-vectors 1 1 BFMLS (multiple and single vector) Four ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 Decode fields Instruction page Encoding sz U S op 0 0 0 SMLALL (multiple and single vector) Two ZA quad-vectors 0 1 0 SMLSLL (multiple and single vector) Two ZA quad-vectors 1 0 0 UMLALL (multiple and single vector) Two ZA quad-vectors 1 1 0 UMLSLL (multiple and single vector) Two ZA quad-vectors 0 1 1 UNALLOCATED 0 0 0 1 USMLALL (multiple and single vector) Two ZA quad-vectors 0 1 0 1 SUMLALL (multiple and single vector) Two ZA quad-vectors 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 Instruction page Encoding FMLALL (multiple and single vector) Two ZA quad-vectors 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 Decode fields Instruction page Encoding sz U S op 0 0 0 SMLALL (multiple and single vector) One ZA quad-vector 0 1 0 SMLSLL (multiple and single vector) One ZA quad-vector 1 0 0 UMLALL (multiple and single vector) One ZA quad-vector 1 1 0 UMLSLL (multiple and single vector) One ZA quad-vector 0 0 0 1 USMLALL (multiple and single vector) One ZA quad-vector 0 0 1 1 UNALLOCATED 0 1 1 UNALLOCATED 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding op S o2 0 0 0 FMLAL (multiple and single vector, FP16 to FP32) Two ZA double-vectors 0 0 1 FMLAL (multiple and single vector, FP8 to FP16) Two ZA double-vectors 0 1 0 FMLSL (multiple and single vector) Two ZA double-vectors 0 1 1 UNALLOCATED 1 1 UNALLOCATED 1 0 0 BFMLAL (multiple and single vector) Two ZA double-vectors 1 1 0 BFMLSL (multiple and single vector) Two ZA double-vectors 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 0 Decode fields Instruction page Encoding U S op 1 UNALLOCATED 0 0 0 SMLAL (multiple and single vector) Two ZA double-vectors 0 1 0 SMLSL (multiple and single vector) Two ZA double-vectors 1 0 0 UMLAL (multiple and single vector) Two ZA double-vectors 1 1 0 UMLSL (multiple and single vector) Two ZA double-vectors 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 Decode fields Instruction page Encoding op S 0 0 FMLAL (multiple and single vector, FP16 to FP32) One ZA double-vector 0 1 FMLSL (multiple and single vector) One ZA double-vector 1 0 BFMLAL (multiple and single vector) One ZA double-vector 1 1 BFMLSL (multiple and single vector) One ZA double-vector 1 1 0 0 0 0 0 1 0 1 1 0 0 0 1 1 Decode fields Instruction page Encoding U S 0 0 SMLAL (multiple and single vector) One ZA double-vector 0 1 SMLSL (multiple and single vector) One ZA double-vector 1 0 UMLAL (multiple and single vector) One ZA double-vector 1 1 UMLSL (multiple and single vector) One ZA double-vector 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 Decode fields Instruction page Encoding opc 00 FDOT (2-way, multiple and single vector, FP16 to FP32) Two ZA single-vectors 01 FDOT (2-way, multiple and single vector, FP8 to FP16) Two ZA single-vectors 10 BFDOT (multiple and single vector) Two ZA single-vectors 11 FDOT (4-way, multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 0 1 0 1 0 Decode fields Instruction page Encoding U 0 SDOT (4-way, multiple and single vector) Two ZA single-vectors 1 UDOT (4-way, multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 Decode fields Instruction page Encoding U 0 USDOT (4-way, multiple and single vector) Two ZA single-vectors 1 SUDOT (4-way, multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1 Decode fields Instruction page Encoding U 0 SDOT (2-way, multiple and single vector) Two ZA single-vectors 1 UDOT (2-way, multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 Decode fields Instruction page Encoding S 0 FMLA (multiple and single vector) Two ZA single-vectors 1 FMLS (multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 Decode fields Instruction page Encoding S 0 ADD (to array, multiple and single vector) Two ZA single-vectors 1 SUB (to array, multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 Decode fields Instruction page Encoding sz S 0 0 FMLA (multiple and single vector) Two ZA single-vectors of half-precision elements 0 1 FMLS (multiple and single vector) Two ZA single-vectors of half-precision elements 1 0 BFMLA (multiple and single vector) Two ZA single-vectors 1 1 BFMLS (multiple and single vector) Two ZA single-vectors 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op U 0 0 SMAX (multiple and single vector) Four registers 0 1 UMAX (multiple and single vector) Four registers 1 0 SMIN (multiple and single vector) Four registers 1 1 UMIN (multiple and single vector) Four registers 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 0 0 0 Decode fields Instruction page Encoding size op o2 00 0 0 BFMAX (multiple and single vector) Four registers 00 0 1 BFMIN (multiple and single vector) Four registers 00 1 0 BFMAXNM (multiple and single vector) Four registers 00 1 1 BFMINNM (multiple and single vector) Four registers != 00 0 0 FMAX (multiple and single vector) Four registers != 00 0 1 FMIN (multiple and single vector) Four registers != 00 1 0 FMAXNM (multiple and single vector) Four registers != 00 1 1 FMINNM (multiple and single vector) Four registers 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 Decode fields Instruction page Encoding size op 1 UNALLOCATED 00 0 BFSCALE (multiple and single vector) Four registers != 00 0 FSCALE (multiple and single vector) Four registers 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 Decode fields Instruction page Encoding opc U 001 0 SRSHL (multiple and single vector) Four registers 001 1 URSHL (multiple and single vector) Four registers != 001 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 Decode fields Instruction page Encoding op 0 ADD (to vector, multiple vectors) Four registers 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op 0 SQDMULH (multiple and single vector) Four registers 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding op U 0 0 SMAX (multiple and single vector) Two registers 0 1 UMAX (multiple and single vector) Two registers 1 0 SMIN (multiple and single vector) Two registers 1 1 UMIN (multiple and single vector) Two registers 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 Decode fields Instruction page Encoding size op o2 00 0 0 BFMAX (multiple and single vector) Two registers 00 0 1 BFMIN (multiple and single vector) Two registers 00 1 0 BFMAXNM (multiple and single vector) Two registers 00 1 1 BFMINNM (multiple and single vector) Two registers != 00 0 0 FMAX (multiple and single vector) Two registers != 00 0 1 FMIN (multiple and single vector) Two registers != 00 1 0 FMAXNM (multiple and single vector) Two registers != 00 1 1 FMINNM (multiple and single vector) Two registers 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 Decode fields Instruction page Encoding size op 1 UNALLOCATED 00 0 BFSCALE (multiple and single vector) Two registers != 00 0 FSCALE (multiple and single vector) Two registers 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 Decode fields Instruction page Encoding opc U 001 0 SRSHL (multiple and single vector) Two registers 001 1 URSHL (multiple and single vector) Two registers != 001 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 Decode fields Instruction page Encoding op 0 ADD (to vector, multiple vectors) Two registers 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 Decode fields Instruction page Encoding op 0 SQDMULH (multiple and single vector) Two registers 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 Decode fields Instruction page Encoding size op 1 UNALLOCATED 00 0 BFCLAMP Two registers != 00 0 FCLAMP Two registers 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 Decode fields Instruction page Encoding U 0 SCLAMP Two registers 1 UCLAMP Two registers 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 0 Decode fields Instruction page Encoding size op 1 UNALLOCATED 00 0 BFCLAMP Four registers != 00 0 FCLAMP Four registers 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 Decode fields Instruction page Encoding U 0 SCLAMP Four registers 1 UCLAMP Four registers 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 Decode fields Instruction page Encoding op 0 ZIP (two registers) 8-bit to 64-bit elements 1 UZP (two registers) 8-bit to 64-bit elements 1 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0 1 Decode fields Instruction page Encoding op 0 ZIP (two registers) 128-bit element 1 UZP (two registers) 128-bit element 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 Decode fields Instruction page Encoding op U 0 0 SQRSHR (two registers) 0 1 UQRSHR (two registers) 1 0 SQRSHRU (two registers) 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 1 1 1 0 1 1 Decode fields Instruction page Encoding N op U 1 1 UNALLOCATED 0 0 0 SQRSHR (four registers) 0 0 1 UQRSHR (four registers) 0 1 0 SQRSHRU (four registers) 1 0 0 SQRSHRN 1 0 1 UQRSHRN 1 1 0 SQRSHRUN 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 Decode fields Instruction page Encoding op N 0 0 FCVT (narrowing, FP32 to FP16) 0 1 FCVTN (FP32 to FP16) 1 0 BFCVT (single-precision to BFloat16) 1 1 BFCVTN 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 Decode fields Instruction page Encoding U 0 FCVTZS Two registers 1 FCVTZU Two registers 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding U 0 SCVTF Two registers 1 UCVTF Two registers 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 Decode fields Instruction page Encoding op U 0 0 SQCVT (two registers) 0 1 UQCVT (two registers) 1 0 SQCVTU (two registers) 1 1 UNALLOCATED 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding op 0 FCVT (narrowing, FP16 to FP8) 1 BFCVT (BFloat16 to 8-bit floating-point) 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 0 Decode fields Instruction page Encoding U 0 SUNPK Two registers 1 UUNPK Two registers 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 0 0 0 Decode fields Instruction page Encoding opc L 00 0 F1CVT, F2CVT F1CVT 00 1 F1CVTL, F2CVTL F1CVTL 01 0 BF1CVT, BF2CVT BF1CVT 01 1 BF1CVTL, BF2CVTL BF1CVTL 10 0 F1CVT, F2CVT F2CVT 10 1 F1CVTL, F2CVTL F2CVTL 11 0 BF1CVT, BF2CVT BF2CVT 11 1 BF1CVTL, BF2CVTL BF2CVTL 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 Decode fields Instruction page Encoding size opc 10 000 FRINTN Two registers 10 001 FRINTP Two registers 10 010 FRINTM Two registers 10 011 UNALLOCATED 10 100 FRINTA Two registers 10 101 UNALLOCATED 10 11x UNALLOCATED != 10 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 Decode fields Instruction page Encoding L 0 FCVT (widening) 1 FCVTL 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding U 0 FCVTZS Four registers 1 FCVTZU Four registers 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding U 0 SCVTF Four registers 1 UCVTF Four registers 1 1 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 Decode fields Instruction page Encoding op N U 0 0 0 SQCVT (four registers) 0 0 1 UQCVT (four registers) 0 1 0 SQCVTN 0 1 1 UQCVTN 1 1 UNALLOCATED 1 0 0 SQCVTU (four registers) 1 1 0 SQCVTUN 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding N 0 FCVT (narrowing, FP32 to FP8) 1 FCVTN (FP32 to FP8) 1 1 0 0 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 Decode fields Instruction page Encoding U 0 SUNPK Four registers 1 UUNPK Four registers 1 1 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op 0 ZIP (four registers) 8-bit to 64-bit elements 1 UZP (four registers) 8-bit to 64-bit elements 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op 0 ZIP (four registers) 128-bit element 1 UZP (four registers) 128-bit element 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size opc 10 000 FRINTN Four registers 10 001 FRINTP Four registers 10 010 FRINTM Four registers 10 011 UNALLOCATED 10 100 FRINTA Four registers 10 101 UNALLOCATED 10 11x UNALLOCATED != 10 UNALLOCATED 1 1 0 0 0 0 0 1 1 0 1 0 0 0 0 Instruction page Encoding SEL Two registers 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 Instruction page Encoding SEL Four registers 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding opc opc2 x1x 1xx UNALLOCATED 000 ZERO (single-vector) Two ZA single-vectors 001 ZERO (double-vector) One ZA double-vector 010 0xx ZERO (double-vector) Two ZA double-vectors 011 0xx ZERO (double-vector) Four ZA double-vectors 100 ZERO (single-vector) Four ZA single-vectors 101 0xx ZERO (quad-vector) One ZA quad-vector 101 1xx UNALLOCATED 11x 01x UNALLOCATED 110 00x ZERO (quad-vector) Two ZA quad-vectors 111 00x ZERO (quad-vector) Four ZA quad-vectors 1 1 0 0 0 0 0 1 1 0 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding size 00 BFMUL (multiple and single vector) Two registers != 00 FMUL (multiple and single vector) Two registers 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 Decode fields Instruction page Encoding size 00 BFMUL (multiple and single vector) Four registers != 00 FMUL (multiple and single vector) Four registers 1 0 0 0 0 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding S 0 BMOPA 1 BMOPS 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 Instruction page Encoding FMOPA (widening, 2-way, FP8 to FP16) 1 0 0 0 0 0 0 1 1 0 0 1 0 0 Decode fields Instruction page Encoding S 0 FMOPA (non-widening) Half-precision 1 FMOPS (non-widening) Half-precision 1 0 0 0 0 0 0 1 1 0 1 1 0 0 Decode fields Instruction page Encoding S 0 BFMOPA (non-widening) 1 BFMOPS (non-widening) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding M N S 0 0 0 FMOP4A (non-widening) Single-precision, single vectors 0 0 1 FMOP4S (non-widening) Single-precision, single vectors 0 1 0 FMOP4A (non-widening) Single-precision, multiple and single vectors 0 1 1 FMOP4S (non-widening) Single-precision, multiple and single vectors 1 0 0 FMOP4A (non-widening) Single-precision, single and multiple vectors 1 0 1 FMOP4S (non-widening) Single-precision, single and multiple vectors 1 1 0 FMOP4A (non-widening) Single-precision, multiple vectors 1 1 1 FMOP4S (non-widening) Single-precision, multiple vectors 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding M N 0 0 FMOP4A (widening, 4-way) Single vectors 0 1 FMOP4A (widening, 4-way) Multiple and single vectors 1 0 FMOP4A (widening, 4-way) Single and multiple vectors 1 1 FMOP4A (widening, 4-way) Multiple vectors 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding M N S 0 0 0 BFMOP4A (widening) Single vectors 0 0 1 BFMOP4S (widening) Single vectors 0 1 0 BFMOP4A (widening) Multiple and single vectors 0 1 1 BFMOP4S (widening) Multiple and single vectors 1 0 0 BFMOP4A (widening) Single and multiple vectors 1 0 1 BFMOP4S (widening) Single and multiple vectors 1 1 0 BFMOP4A (widening) Multiple vectors 1 1 1 BFMOP4S (widening) Multiple vectors 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding M N S 0 0 0 FMOP4A (widening, 2-way, FP16 to FP32) Single vectors 0 0 1 FMOP4S (widening) Single vectors 0 1 0 FMOP4A (widening, 2-way, FP16 to FP32) Multiple and single vectors 0 1 1 FMOP4S (widening) Multiple and single vectors 1 0 0 FMOP4A (widening, 2-way, FP16 to FP32) Single and multiple vectors 1 0 1 FMOP4S (widening) Single and multiple vectors 1 1 0 FMOP4A (widening, 2-way, FP16 to FP32) Multiple vectors 1 1 1 FMOP4S (widening) Multiple vectors 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding u0 u1 M N S 0 0 0 0 0 SMOP4A (4-way) 32-bit, single vectors 0 0 0 0 1 SMOP4S (4-way) 32-bit, single vectors 0 0 0 1 0 SMOP4A (4-way) 32-bit, multiple and single vectors 0 0 0 1 1 SMOP4S (4-way) 32-bit, multiple and single vectors 0 0 1 0 0 SMOP4A (4-way) 32-bit, single and multiple vectors 0 0 1 0 1 SMOP4S (4-way) 32-bit, single and multiple vectors 0 0 1 1 0 SMOP4A (4-way) 32-bit, multiple vectors 0 0 1 1 1 SMOP4S (4-way) 32-bit, multiple vectors 0 1 0 0 0 SUMOP4A 32-bit, single vectors 0 1 0 0 1 SUMOP4S 32-bit, single vectors 0 1 0 1 0 SUMOP4A 32-bit, multiple and single vectors 0 1 0 1 1 SUMOP4S 32-bit, multiple and single vectors 0 1 1 0 0 SUMOP4A 32-bit, single and multiple vectors 0 1 1 0 1 SUMOP4S 32-bit, single and multiple vectors 0 1 1 1 0 SUMOP4A 32-bit, multiple vectors 0 1 1 1 1 SUMOP4S 32-bit, multiple vectors 1 0 0 0 0 USMOP4A 32-bit, single vectors 1 0 0 0 1 USMOP4S 32-bit, single vectors 1 0 0 1 0 USMOP4A 32-bit, multiple and single vectors 1 0 0 1 1 USMOP4S 32-bit, multiple and single vectors 1 0 1 0 0 USMOP4A 32-bit, single and multiple vectors 1 0 1 0 1 USMOP4S 32-bit, single and multiple vectors 1 0 1 1 0 USMOP4A 32-bit, multiple vectors 1 0 1 1 1 USMOP4S 32-bit, multiple vectors 1 1 0 0 0 UMOP4A (4-way) 32-bit, single vectors 1 1 0 0 1 UMOP4S (4-way) 32-bit, single vectors 1 1 0 1 0 UMOP4A (4-way) 32-bit, multiple and single vectors 1 1 0 1 1 UMOP4S (4-way) 32-bit, multiple and single vectors 1 1 1 0 0 UMOP4A (4-way) 32-bit, single and multiple vectors 1 1 1 0 1 UMOP4S (4-way) 32-bit, single and multiple vectors 1 1 1 1 0 UMOP4A (4-way) 32-bit, multiple vectors 1 1 1 1 1 UMOP4S (4-way) 32-bit, multiple vectors 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 Decode fields Instruction page Encoding M N 0 0 FMOP4A (widening, 2-way, FP8 to FP16) Single vectors 0 1 FMOP4A (widening, 2-way, FP8 to FP16) Multiple and single vectors 1 0 FMOP4A (widening, 2-way, FP8 to FP16) Single and multiple vectors 1 1 FMOP4A (widening, 2-way, FP8 to FP16) Multiple vectors 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Decode fields Instruction page Encoding M N S 0 0 0 FMOP4A (non-widening) Half-precision, single vectors 0 0 1 FMOP4S (non-widening) Half-precision, single vectors 0 1 0 FMOP4A (non-widening) Half-precision, multiple and single vectors 0 1 1 FMOP4S (non-widening) Half-precision, multiple and single vectors 1 0 0 FMOP4A (non-widening) Half-precision, single and multiple vectors 1 0 1 FMOP4S (non-widening) Half-precision, single and multiple vectors 1 1 0 FMOP4A (non-widening) Half-precision, multiple vectors 1 1 1 FMOP4S (non-widening) Half-precision, multiple vectors 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 Decode fields Instruction page Encoding M N S 0 0 0 BFMOP4A (non-widening) Single vectors 0 0 1 BFMOP4S (non-widening) Single vectors 0 1 0 BFMOP4A (non-widening) Multiple and single vectors 0 1 1 BFMOP4S (non-widening) Multiple and single vectors 1 0 0 BFMOP4A (non-widening) Single and multiple vectors 1 0 1 BFMOP4S (non-widening) Single and multiple vectors 1 1 0 BFMOP4A (non-widening) Multiple vectors 1 1 1 BFMOP4S (non-widening) Multiple vectors 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 Decode fields Instruction page Encoding u0 M N S 0 0 0 0 SMOP4A (2-way) Single vectors 0 0 0 1 SMOP4S (2-way) Single vectors 0 0 1 0 SMOP4A (2-way) Multiple and single vectors 0 0 1 1 SMOP4S (2-way) Multiple and single vectors 0 1 0 0 SMOP4A (2-way) Single and multiple vectors 0 1 0 1 SMOP4S (2-way) Single and multiple vectors 0 1 1 0 SMOP4A (2-way) Multiple vectors 0 1 1 1 SMOP4S (2-way) Multiple vectors 1 0 0 0 UMOP4A (2-way) Single vectors 1 0 0 1 UMOP4S (2-way) Single vectors 1 0 1 0 UMOP4A (2-way) Multiple and single vectors 1 0 1 1 UMOP4S (2-way) Multiple and single vectors 1 1 0 0 UMOP4A (2-way) Single and multiple vectors 1 1 0 1 UMOP4S (2-way) Single and multiple vectors 1 1 1 0 UMOP4A (2-way) Multiple vectors 1 1 1 1 UMOP4S (2-way) Multiple vectors 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 Decode fields Instruction page Encoding M N S 0 0 0 FMOP4A (non-widening) Double-precision, single vectors 0 0 1 FMOP4S (non-widening) Double-precision, single vectors 0 1 0 FMOP4A (non-widening) Double-precision, multiple and single vectors 0 1 1 FMOP4S (non-widening) Double-precision, multiple and single vectors 1 0 0 FMOP4A (non-widening) Double-precision, single and multiple vectors 1 0 1 FMOP4S (non-widening) Double-precision, single and multiple vectors 1 1 0 FMOP4A (non-widening) Double-precision, multiple vectors 1 1 1 FMOP4S (non-widening) Double-precision, multiple vectors 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 Decode fields Instruction page Encoding u0 u1 M N S 0 0 0 0 0 SMOP4A (4-way) 64-bit, single vectors 0 0 0 0 1 SMOP4S (4-way) 64-bit, single vectors 0 0 0 1 0 SMOP4A (4-way) 64-bit, multiple and single vectors 0 0 0 1 1 SMOP4S (4-way) 64-bit, multiple and single vectors 0 0 1 0 0 SMOP4A (4-way) 64-bit, single and multiple vectors 0 0 1 0 1 SMOP4S (4-way) 64-bit, single and multiple vectors 0 0 1 1 0 SMOP4A (4-way) 64-bit, multiple vectors 0 0 1 1 1 SMOP4S (4-way) 64-bit, multiple vectors 0 1 0 0 0 SUMOP4A 64-bit, single vectors 0 1 0 0 1 SUMOP4S 64-bit, single vectors 0 1 0 1 0 SUMOP4A 64-bit, multiple and single vectors 0 1 0 1 1 SUMOP4S 64-bit, multiple and single vectors 0 1 1 0 0 SUMOP4A 64-bit, single and multiple vectors 0 1 1 0 1 SUMOP4S 64-bit, single and multiple vectors 0 1 1 1 0 SUMOP4A 64-bit, multiple vectors 0 1 1 1 1 SUMOP4S 64-bit, multiple vectors 1 0 0 0 0 USMOP4A 64-bit, single vectors 1 0 0 0 1 USMOP4S 64-bit, single vectors 1 0 0 1 0 USMOP4A 64-bit, multiple and single vectors 1 0 0 1 1 USMOP4S 64-bit, multiple and single vectors 1 0 1 0 0 USMOP4A 64-bit, single and multiple vectors 1 0 1 0 1 USMOP4S 64-bit, single and multiple vectors 1 0 1 1 0 USMOP4A 64-bit, multiple vectors 1 0 1 1 1 USMOP4S 64-bit, multiple vectors 1 1 0 0 0 UMOP4A (4-way) 64-bit, single vectors 1 1 0 0 1 UMOP4S (4-way) 64-bit, single vectors 1 1 0 1 0 UMOP4A (4-way) 64-bit, multiple and single vectors 1 1 0 1 1 UMOP4S (4-way) 64-bit, multiple and single vectors 1 1 1 0 0 UMOP4A (4-way) 64-bit, single and multiple vectors 1 1 1 0 1 UMOP4S (4-way) 64-bit, single and multiple vectors 1 1 1 1 0 UMOP4A (4-way) 64-bit, multiple vectors 1 1 1 1 1 UMOP4S (4-way) 64-bit, multiple vectors 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Instruction page Encoding FTMOPA (non-widening) Single-precision 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Instruction page Encoding FTMOPA (widening, 4-way) 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 Instruction page Encoding BFTMOPA (widening) 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 Instruction page Encoding FTMOPA (widening, 2-way, FP16 to FP32) 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Decode fields Instruction page Encoding u0 u1 0 0 STMOPA (4-way) 0 1 SUTMOPA 1 0 USTMOPA 1 1 UTMOPA (4-way) 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 Instruction page Encoding FTMOPA (widening, 2-way, FP8 to FP16) 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 Instruction page Encoding FTMOPA (non-widening) Half-precision 1 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 Instruction page Encoding BFTMOPA (non-widening) 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 Decode fields Instruction page Encoding u0 0 STMOPA (2-way) 1 UTMOPA (2-way) 1 1 0 0 0 0 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding op0 opc 00000000000000 0001 ZERO (table) 00000000000000 != 0001 UNALLOCATED != 00000000000000 UNALLOCATED SVE encodings 0 0 0 0 0 1 0 0 1 1 0 1 0 Decode fields Instruction page Encoding opc 00 ADR Unpacked 32-bit signed offsets 01 ADR Unpacked 32-bit unsigned offsets 1x ADR Packed offsets 0 0 0 0 0 1 0 1 != 11 0 0 0 0 Decode fields Instruction page Encoding opc 00 ORR (immediate) 01 EOR (immediate) 10 AND (immediate) 0 0 0 0 0 1 0 1 1 1 0 0 0 0 Instruction page Encoding DUPM 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 Decode fields Instruction page Encoding opc 00 AND (vectors, unpredicated) 01 ORR (vectors, unpredicated) 10 EOR (vectors, unpredicated) 11 BIC (vectors, unpredicated) 0 0 0 0 0 1 0 0 1 0 0 1 1 0 1 Instruction page Encoding XAR 0 0 0 0 0 1 0 0 1 0 0 1 1 1 Decode fields Instruction page Encoding opc o2 00 0 EOR3 00 1 BSL 01 0 BCAX 01 1 BSL1N 1x 0 UNALLOCATED 10 1 BSL2N 11 1 NBSL 0 0 0 0 0 1 0 0 0 0 1 0 0 Decode fields Instruction page Encoding opc L U 00 0 0 ASR (immediate, predicated) 00 0 1 LSR (immediate, predicated) 00 1 0 UNALLOCATED 00 1 1 LSL (immediate, predicated) 01 0 0 ASRD 01 0 1 UNALLOCATED 01 1 0 SQSHL (immediate) 01 1 1 UQSHL (immediate) 10 UNALLOCATED 11 0 0 SRSHR 11 0 1 URSHR 11 1 0 UNALLOCATED 11 1 1 SQSHLU 0 0 0 0 0 1 0 0 0 1 0 1 0 0 Decode fields Instruction page Encoding R L U 1 0 UNALLOCATED 0 0 0 ASR (vectors) 0 0 1 LSR (vectors) 0 1 1 LSL (vectors) 1 0 0 ASRR 1 0 1 LSRR 1 1 1 LSLR 0 0 0 0 0 1 0 0 0 1 1 1 0 0 Decode fields Instruction page Encoding R L U 0 0 0 ASR (wide elements, predicated) 0 0 1 LSR (wide elements, predicated) 0 1 0 UNALLOCATED 0 1 1 LSL (wide elements, predicated) 1 UNALLOCATED 0 0 0 0 0 1 0 0 1 1 0 0 0 Decode fields Instruction page Encoding opc 00 ASR (wide elements, unpredicated) 01 LSR (wide elements, unpredicated) 10 UNALLOCATED 11 LSL (wide elements, unpredicated) 0 0 0 0 0 1 0 0 1 1 0 0 1 Decode fields Instruction page Encoding opc 00 ASR (immediate, unpredicated) 01 LSR (immediate, unpredicated) 10 UNALLOCATED 11 LSL (immediate, unpredicated) 0 0 0 0 0 1 0 0 1 0 1 1 0 0 Decode fields Instruction page Encoding size D U 00 UNALLOCATED 01 0 0 SQINCH (vector) 01 0 1 UQINCH (vector) 01 1 0 SQDECH (vector) 01 1 1 UQDECH (vector) 10 0 0 SQINCW (vector) 10 0 1 UQINCW (vector) 10 1 0 SQDECW (vector) 10 1 1 UQDECW (vector) 11 0 0 SQINCD (vector) 11 0 1 UQINCD (vector) 11 1 0 SQDECD (vector) 11 1 1 UQDECD (vector) 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 Decode fields Instruction page Encoding size D 00 UNALLOCATED 01 0 INCD, INCH, INCW (vector) Halfword 01 1 DECD, DECH, DECW (vector) Halfword 10 0 INCD, INCH, INCW (vector) Word 10 1 DECD, DECH, DECW (vector) Word 11 0 INCD, INCH, INCW (vector) Doubleword 11 1 DECD, DECH, DECW (vector) Doubleword 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 Decode fields Instruction page Encoding size op 1 UNALLOCATED 00 0 CNTB, CNTD, CNTH, CNTW Byte 01 0 CNTB, CNTD, CNTH, CNTW Halfword 10 0 CNTB, CNTD, CNTH, CNTW Word 11 0 CNTB, CNTD, CNTH, CNTW Doubleword 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 Decode fields Instruction page Encoding size D 00 0 INCB, INCD, INCH, INCW (scalar) Byte 00 1 DECB, DECD, DECH, DECW (scalar) Byte 01 0 INCB, INCD, INCH, INCW (scalar) Halfword 01 1 DECB, DECD, DECH, DECW (scalar) Halfword 10 0 INCB, INCD, INCH, INCW (scalar) Word 10 1 DECB, DECD, DECH, DECW (scalar) Word 11 0 INCB, INCD, INCH, INCW (scalar) Doubleword 11 1 DECB, DECD, DECH, DECW (scalar) Doubleword 0 0 0 0 0 1 0 0 1 1 1 1 1 Decode fields Instruction page Encoding size sf D U 00 0 0 0 SQINCB 32-bit 00 0 0 1 UQINCB 32-bit 00 0 1 0 SQDECB 32-bit 00 0 1 1 UQDECB 32-bit 00 1 0 0 SQINCB 64-bit 00 1 0 1 UQINCB 64-bit 00 1 1 0 SQDECB 64-bit 00 1 1 1 UQDECB 64-bit 01 0 0 0 SQINCH (scalar) 32-bit 01 0 0 1 UQINCH (scalar) 32-bit 01 0 1 0 SQDECH (scalar) 32-bit 01 0 1 1 UQDECH (scalar) 32-bit 01 1 0 0 SQINCH (scalar) 64-bit 01 1 0 1 UQINCH (scalar) 64-bit 01 1 1 0 SQDECH (scalar) 64-bit 01 1 1 1 UQDECH (scalar) 64-bit 10 0 0 0 SQINCW (scalar) 32-bit 10 0 0 1 UQINCW (scalar) 32-bit 10 0 1 0 SQDECW (scalar) 32-bit 10 0 1 1 UQDECW (scalar) 32-bit 10 1 0 0 SQINCW (scalar) 64-bit 10 1 0 1 UQINCW (scalar) 64-bit 10 1 1 0 SQDECW (scalar) 64-bit 10 1 1 1 UQDECW (scalar) 64-bit 11 0 0 0 SQINCD (scalar) 32-bit 11 0 0 1 UQINCD (scalar) 32-bit 11 0 1 0 SQDECD (scalar) 32-bit 11 0 1 1 UQDECD (scalar) 32-bit 11 1 0 0 SQINCD (scalar) 64-bit 11 1 0 1 UQINCD (scalar) 64-bit 11 1 1 0 SQDECD (scalar) 64-bit 11 1 1 1 UQDECD (scalar) 64-bit 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 Decode fields Instruction page Encoding size 00 BFCLAMP != 00 FCLAMP 0 0 1 0 0 1 0 1 1 0 1 0 1 0 0 0 0 Decode fields Instruction page Encoding D U opc != 00 UNALLOCATED 0 0 00 SQINCP (vector) 0 1 00 UQINCP (vector) 1 0 00 SQDECP (vector) 1 1 00 UQDECP (vector) 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding op D opc2 0 != 00 UNALLOCATED 0 0 00 INCP (vector) 0 1 00 DECP (vector) 1 UNALLOCATED 0 0 1 0 0 1 0 1 1 0 1 0 1 0 0 0 1 Decode fields Instruction page Encoding D U sf op 1 UNALLOCATED 0 0 0 0 SQINCP (scalar) 32-bit 0 0 1 0 SQINCP (scalar) 64-bit 0 1 0 0 UQINCP (scalar) 32-bit 0 1 1 0 UQINCP (scalar) 64-bit 1 0 0 0 SQDECP (scalar) 32-bit 1 0 1 0 SQDECP (scalar) 64-bit 1 1 0 0 UQDECP (scalar) 32-bit 1 1 1 0 UQDECP (scalar) 64-bit 0 0 1 0 0 1 0 1 1 0 1 1 1 0 0 0 1 Decode fields Instruction page Encoding op D opc2 0 != 00 UNALLOCATED 0 0 00 INCP (scalar) 0 1 00 DECP (scalar) 1 UNALLOCATED 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 Instruction page Encoding INDEX (immediates) 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 Instruction page Encoding INDEX (scalar, immediate) 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 Instruction page Encoding INDEX (immediate, scalar) 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 Instruction page Encoding INDEX (scalars) 0 0 0 0 0 1 0 0 1 0 0 0 Decode fields Instruction page Encoding size opc 000 ADD (vectors, unpredicated) 001 SUB (vectors, unpredicated) 100 SQADD (vectors, unpredicated) 101 UQADD (vectors, unpredicated) 110 SQSUB (vectors, unpredicated) 111 UQSUB (vectors, unpredicated) 11 010 ADDPT (unpredicated) 11 011 SUBPT (unpredicated) != 11 01x UNALLOCATED 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size opc 000 ADD (vectors, predicated) 001 SUB (vectors, predicated) 010 UNALLOCATED 011 SUBR (vectors) 11 100 ADDPT (predicated) 11 101 SUBPT (predicated) 11 11x UNALLOCATED != 11 1xx UNALLOCATED 0 0 0 0 0 1 0 0 0 0 1 0 0 0 Decode fields Instruction page Encoding opc U 00 0 SMAX (vectors) 00 1 UMAX (vectors) 01 0 SMIN (vectors) 01 1 UMIN (vectors) 10 0 SABD 10 1 UABD 11 UNALLOCATED 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 Decode fields Instruction page Encoding H U 0 0 MUL (vectors, predicated) 0 1 UNALLOCATED 1 0 SMULH (predicated) 1 1 UMULH (predicated) 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 Decode fields Instruction page Encoding R U 0 0 SDIV 0 1 UDIV 1 0 SDIVR 1 1 UDIVR 0 0 0 0 0 1 0 0 0 1 1 0 0 0 Decode fields Instruction page Encoding opc 000 ORR (vectors, predicated) 001 EOR (vectors, predicated) 010 AND (vectors, predicated) 011 BIC (vectors, predicated) 1xx UNALLOCATED 0 0 1 0 0 1 0 1 1 0 0 0 Decode fields Instruction page Encoding U lt eq 0 0 0 WHILEGE (predicate) 0 0 1 WHILEGT (predicate) 0 1 0 WHILELT (predicate) 0 1 1 WHILELE (predicate) 1 0 0 WHILEHS (predicate) 1 0 1 WHILEHI (predicate) 1 1 0 WHILELO (predicate) 1 1 1 WHILELS (predicate) 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding op ne 0 UNALLOCATED 1 0 CTERMEQ, CTERMNE Equal 1 1 CTERMEQ, CTERMNE Not equal 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 Decode fields Instruction page Encoding rw 0 WHILEWR 1 WHILERW 0 0 1 0 0 1 0 1 0 0 Decode fields Instruction page Encoding op o2 ne 0 0 0 CMP<cc> (immediate) Greater than or equal 0 0 1 CMP<cc> (immediate) Greater than 0 1 0 CMP<cc> (immediate) Less than 0 1 1 CMP<cc> (immediate) Less than or equal 1 0 0 CMP<cc> (immediate) Equal 1 0 1 CMP<cc> (immediate) Not equal 1 1 UNALLOCATED 0 0 1 0 0 1 0 0 1 Decode fields Instruction page Encoding lt ne 0 0 CMP<cc> (immediate) Higher or same 0 1 CMP<cc> (immediate) Higher 1 0 CMP<cc> (immediate) Lower 1 1 CMP<cc> (immediate) Lower or same 0 0 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding op o2 ne 0 0 0 CMP<cc> (vectors) Higher or same 0 0 1 CMP<cc> (vectors) Higher 0 1 0 CMP<cc> (wide elements) Equal 0 1 1 CMP<cc> (wide elements) Not equal 1 0 0 CMP<cc> (vectors) Greater than or equal 1 0 1 CMP<cc> (vectors) Greater than 1 1 0 CMP<cc> (vectors) Equal 1 1 1 CMP<cc> (vectors) Not equal 0 0 1 0 0 1 0 0 0 1 Decode fields Instruction page Encoding U lt ne 0 0 0 CMP<cc> (wide elements) Greater than or equal 0 0 1 CMP<cc> (wide elements) Greater than 0 1 0 CMP<cc> (wide elements) Less than 0 1 1 CMP<cc> (wide elements) Less than or equal 1 0 0 CMP<cc> (wide elements) Higher or same 1 0 1 CMP<cc> (wide elements) Higher 1 1 0 CMP<cc> (wide elements) Lower 1 1 1 CMP<cc> (wide elements) Lower or same 0 0 0 0 0 1 0 0 1 1 0 1 1 0 Decode fields Instruction page Encoding op 0 FTSSEL 1 UNALLOCATED 0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 Decode fields Instruction page Encoding opc 00000 FEXPA != 00000 UNALLOCATED 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 Decode fields Instruction page Encoding opc opc2 00 00000 MOVPRFX (unpredicated) 00 != 00000 UNALLOCATED != 00 UNALLOCATED 0 0 0 0 0 1 0 0 0 0 1 Decode fields Instruction page Encoding op 0 MLA (vectors) 1 MLS (vectors) 0 0 0 0 0 1 0 0 0 1 1 Decode fields Instruction page Encoding op 0 MAD 1 MSB 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size U 0x UNALLOCATED 1x 0 SDOT (4-way, vectors) 1x 1 UDOT (4-way, vectors) 0 1 0 0 0 1 0 0 0 0 0 0 0 1 Decode fields Instruction page Encoding S 0 SQDMLALBT 1 SQDMLSLBT 0 1 0 0 0 1 0 0 0 0 0 0 1 Instruction page Encoding CDOT (vectors) 0 1 0 0 0 1 0 0 0 0 0 1 Decode fields Instruction page Encoding op 0 CMLA (vectors) 1 SQRDCMLAH (vectors) 0 1 0 0 0 1 0 0 0 0 1 0 Decode fields Instruction page Encoding S U T 0 0 0 SMLALB (vectors) 0 0 1 SMLALT (vectors) 0 1 0 UMLALB (vectors) 0 1 1 UMLALT (vectors) 1 0 0 SMLSLB (vectors) 1 0 1 SMLSLT (vectors) 1 1 0 UMLSLB (vectors) 1 1 1 UMLSLT (vectors) 0 1 0 0 0 1 0 0 0 0 1 1 0 Decode fields Instruction page Encoding S T 0 0 SQDMLALB (vectors) 0 1 SQDMLALT (vectors) 1 0 SQDMLSLB (vectors) 1 1 SQDMLSLT (vectors) 0 1 0 0 0 1 0 0 0 0 1 1 1 0 Decode fields Instruction page Encoding S 0 SQRDMLAH (vectors) 1 SQRDMLSH (vectors) 0 1 0 0 0 1 0 0 0 0 1 1 1 1 0 Decode fields Instruction page Encoding size 10 USDOT (vectors) != 10 UNALLOCATED 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Decode fields Instruction page Encoding op U 0 0 SADDV 0 1 UADDV 1 UNALLOCATED 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 Decode fields Instruction page Encoding op U 0 0 UNALLOCATED 0 1 ADDQV 1 UNALLOCATED 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 Decode fields Instruction page Encoding op U 0 0 SMAXV 0 1 UMAXV 1 0 SMINV 1 1 UMINV 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 Decode fields Instruction page Encoding op U 0 0 SMAXQV 0 1 UMAXQV 1 0 SMINQV 1 1 UMINQV 0 0 0 0 0 1 0 0 0 1 0 0 0 1 Decode fields Instruction page Encoding opc 00 MOVPRFX (predicated) != 00 UNALLOCATED 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 Decode fields Instruction page Encoding opc 00 ORV 01 EORV 10 ANDV 11 UNALLOCATED 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 Decode fields Instruction page Encoding opc 00 ORQV 01 EORQV 10 ANDQV 11 UNALLOCATED 0 0 0 0 0 1 0 0 0 0 1 0 1 Decode fields Instruction page Encoding M opc 0 000 SXTB, SXTH, SXTW Byte, zeroing 0 001 UXTB, UXTH, UXTW Byte, zeroing 0 010 SXTB, SXTH, SXTW Halfword, zeroing 0 011 UXTB, UXTH, UXTW Halfword, zeroing 0 100 SXTB, SXTH, SXTW Word, zeroing 0 101 UXTB, UXTH, UXTW Word, zeroing 0 110 ABS Zeroing 0 111 NEG Zeroing 1 000 SXTB, SXTH, SXTW Byte, merging 1 001 UXTB, UXTH, UXTW Byte, merging 1 010 SXTB, SXTH, SXTW Halfword, merging 1 011 UXTB, UXTH, UXTW Halfword, merging 1 100 SXTB, SXTH, SXTW Word, merging 1 101 UXTB, UXTH, UXTW Word, merging 1 110 ABS Merging 1 111 NEG Merging 0 0 0 0 0 1 0 0 0 1 1 0 1 Decode fields Instruction page Encoding M opc 111 UNALLOCATED 0 000 CLS Zeroing 0 001 CLZ Zeroing 0 010 CNT Zeroing 0 011 CNOT Zeroing 0 100 FABS Zeroing 0 101 FNEG Zeroing 0 110 NOT (vector) Zeroing 1 000 CLS Merging 1 001 CLZ Merging 1 010 CNT Merging 1 011 CNOT Merging 1 100 FABS Merging 1 101 FNEG Merging 1 110 NOT (vector) Merging 0 0 0 0 0 1 0 1 0 1 0 Decode fields Instruction page Encoding M 0 CPY (immediate, zeroing) 1 CPY (immediate, merging) 0 0 0 0 0 1 0 1 0 1 1 1 0 Instruction page Encoding FCPY 0 0 1 0 0 1 0 1 1 0 0 1 1 Decode fields Instruction page Encoding opc 000 ADD (immediate) 001 SUB (immediate) 010 UNALLOCATED 011 SUBR (immediate) 100 SQADD (immediate) 101 UQADD (immediate) 110 SQSUB (immediate) 111 UQSUB (immediate) 0 0 1 0 0 1 0 1 1 0 1 1 1 Decode fields Instruction page Encoding opc o2 0xx 1 UNALLOCATED 000 0 SMAX (immediate) 001 0 UMAX (immediate) 010 0 SMIN (immediate) 011 0 UMIN (immediate) 1xx UNALLOCATED 0 0 1 0 0 1 0 1 1 1 0 1 1 Decode fields Instruction page Encoding opc o2 000 0 MUL (immediate) 000 1 UNALLOCATED != 000 UNALLOCATED 0 0 1 0 0 1 0 1 1 1 1 0 1 1 Decode fields Instruction page Encoding opc 00 DUP (immediate) != 00 UNALLOCATED 0 0 1 0 0 1 0 1 1 1 1 1 1 1 Decode fields Instruction page Encoding opc o2 00 0 FDUP 00 1 UNALLOCATED != 00 UNALLOCATED 1 0 0 0 0 1 0 != 11 0 0 Decode fields Instruction page Encoding opc U ff 00 0 0 LD1SB (scalar plus vector) 32-bit unscaled offset 00 0 1 LDFF1SB (scalar plus vector) 32-bit unscaled offset 00 1 0 LD1B (scalar plus vector) 32-bit unscaled offset 00 1 1 LDFF1B (scalar plus vector) 32-bit unscaled offset 01 0 0 LD1SH (scalar plus vector) 32-bit unscaled offset 01 0 1 LDFF1SH (scalar plus vector) 32-bit unscaled offset 01 1 0 LD1H (scalar plus vector) 32-bit unscaled offset 01 1 1 LDFF1H (scalar plus vector) 32-bit unscaled offset 10 0 UNALLOCATED 10 1 0 LD1W (scalar plus vector) 32-bit unscaled offset 10 1 1 LDFF1W (scalar plus vector) 32-bit unscaled offset 1 0 0 0 0 1 0 0 0 1 0 0 Decode fields Instruction page Encoding msz 00 PRFB (scalar plus vector) 32-bit scaled offset 01 PRFH (scalar plus vector) 32-bit scaled offset 10 PRFW (scalar plus vector) 32-bit scaled offset 11 PRFD (scalar plus vector) 32-bit scaled offset 1 0 0 0 0 1 0 0 1 1 0 Decode fields Instruction page Encoding U ff 0 0 LD1SH (scalar plus vector) 32-bit scaled offset 0 1 LDFF1SH (scalar plus vector) 32-bit scaled offset 1 0 LD1H (scalar plus vector) 32-bit scaled offset 1 1 LDFF1H (scalar plus vector) 32-bit scaled offset 1 0 0 0 0 1 0 1 0 1 0 Decode fields Instruction page Encoding U ff 0 UNALLOCATED 1 0 LD1W (scalar plus vector) 32-bit scaled offset 1 1 LDFF1W (scalar plus vector) 32-bit scaled offset 1 0 0 0 0 1 0 1 1 0 0 0 0 0 Instruction page Encoding LDR (predicate) 1 0 0 0 0 1 0 1 1 0 0 1 0 Instruction page Encoding LDR (vector) 1 0 0 0 0 1 0 1 1 1 0 0 Decode fields Instruction page Encoding msz 00 PRFB (scalar plus immediate) 01 PRFH (scalar plus immediate) 10 PRFW (scalar plus immediate) 11 PRFD (scalar plus immediate) 1 0 0 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding msz U 00 0 LDNT1SB 32-bit unscaled offset 00 1 LDNT1B (vector plus scalar) 32-bit unscaled offset 01 0 LDNT1SH 32-bit unscaled offset 01 1 LDNT1H (vector plus scalar) 32-bit unscaled offset 10 0 UNALLOCATED 10 1 LDNT1W (vector plus scalar) 32-bit unscaled offset 11 UNALLOCATED 1 0 0 0 0 1 0 0 0 1 1 0 0 Decode fields Instruction page Encoding msz Rm 11111 UNALLOCATED 00 != 11111 PRFB (scalar plus scalar) 01 != 11111 PRFH (scalar plus scalar) 10 != 11111 PRFW (scalar plus scalar) 11 != 11111 PRFD (scalar plus scalar) 1 0 0 0 0 1 0 0 0 1 1 1 0 Decode fields Instruction page Encoding msz 00 PRFB (vector plus immediate) 32-bit element 01 PRFH (vector plus immediate) 32-bit element 10 PRFW (vector plus immediate) 32-bit element 11 PRFD (vector plus immediate) 32-bit element 1 0 0 0 0 1 0 0 1 1 Decode fields Instruction page Encoding msz U ff 00 0 0 LD1SB (vector plus immediate) 32-bit element 00 0 1 LDFF1SB (vector plus immediate) 32-bit element 00 1 0 LD1B (vector plus immediate) 32-bit element 00 1 1 LDFF1B (vector plus immediate) 32-bit element 01 0 0 LD1SH (vector plus immediate) 32-bit element 01 0 1 LDFF1SH (vector plus immediate) 32-bit element 01 1 0 LD1H (vector plus immediate) 32-bit element 01 1 1 LDFF1H (vector plus immediate) 32-bit element 10 0 UNALLOCATED 10 1 0 LD1W (vector plus immediate) 32-bit element 10 1 1 LDFF1W (vector plus immediate) 32-bit element 11 UNALLOCATED 1 0 0 0 0 1 0 1 1 Decode fields Instruction page Encoding dtypeh dtypel 00 00 LD1RB 8-bit element 00 01 LD1RB 16-bit element 00 10 LD1RB 32-bit element 00 11 LD1RB 64-bit element 01 00 LD1RSW 01 01 LD1RH 16-bit element 01 10 LD1RH 32-bit element 01 11 LD1RH 64-bit element 10 00 LD1RSH 64-bit element 10 01 LD1RSH 32-bit element 10 10 LD1RW 32-bit element 10 11 LD1RW 64-bit element 11 00 LD1RSB 64-bit element 11 01 LD1RSB 32-bit element 11 10 LD1RSB 16-bit element 11 11 LD1RD 1 1 0 0 0 1 0 0 0 Decode fields Instruction page Encoding msz U ff 00 0 0 LD1SB (scalar plus vector) 32-bit unpacked unscaled offset 00 0 1 LDFF1SB (scalar plus vector) 32-bit unpacked unscaled offset 00 1 0 LD1B (scalar plus vector) 32-bit unpacked unscaled offset 00 1 1 LDFF1B (scalar plus vector) 32-bit unpacked unscaled offset 01 0 0 LD1SH (scalar plus vector) 32-bit unpacked unscaled offset 01 0 1 LDFF1SH (scalar plus vector) 32-bit unpacked unscaled offset 01 1 0 LD1H (scalar plus vector) 32-bit unpacked unscaled offset 01 1 1 LDFF1H (scalar plus vector) 32-bit unpacked unscaled offset 10 0 0 LD1SW (scalar plus vector) 32-bit unpacked unscaled offset 10 0 1 LDFF1SW (scalar plus vector) 32-bit unpacked unscaled offset 10 1 0 LD1W (scalar plus vector) 32-bit unpacked unscaled offset 10 1 1 LDFF1W (scalar plus vector) 32-bit unpacked unscaled offset 11 0 UNALLOCATED 11 1 0 LD1D (scalar plus vector) 32-bit unpacked unscaled offset 11 1 1 LDFF1D (scalar plus vector) 32-bit unpacked unscaled offset 1 1 0 0 0 1 0 0 0 1 0 0 Decode fields Instruction page Encoding msz 00 PRFB (scalar plus vector) 32-bit unpacked scaled offset 01 PRFH (scalar plus vector) 32-bit unpacked scaled offset 10 PRFW (scalar plus vector) 32-bit unpacked scaled offset 11 PRFD (scalar plus vector) 32-bit unpacked scaled offset 1 1 0 0 0 1 0 != 00 1 0 Decode fields Instruction page Encoding opc U ff 01 0 0 LD1SH (scalar plus vector) 32-bit unpacked scaled offset 01 0 1 LDFF1SH (scalar plus vector) 32-bit unpacked scaled offset 01 1 0 LD1H (scalar plus vector) 32-bit unpacked scaled offset 01 1 1 LDFF1H (scalar plus vector) 32-bit unpacked scaled offset 10 0 0 LD1SW (scalar plus vector) 32-bit unpacked scaled offset 10 0 1 LDFF1SW (scalar plus vector) 32-bit unpacked scaled offset 10 1 0 LD1W (scalar plus vector) 32-bit unpacked scaled offset 10 1 1 LDFF1W (scalar plus vector) 32-bit unpacked scaled offset 11 0 UNALLOCATED 11 1 0 LD1D (scalar plus vector) 32-bit unpacked scaled offset 11 1 1 LDFF1D (scalar plus vector) 32-bit unpacked scaled offset 1 1 0 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding msz U 00 0 LDNT1SB 64-bit unscaled offset 00 1 LDNT1B (vector plus scalar) 64-bit unscaled offset 01 0 LDNT1SH 64-bit unscaled offset 01 1 LDNT1H (vector plus scalar) 64-bit unscaled offset 10 0 LDNT1SW 10 1 LDNT1W (vector plus scalar) 64-bit unscaled offset 11 0 UNALLOCATED 11 1 LDNT1D (vector plus scalar) 1 1 0 0 0 1 0 0 0 1 1 1 0 Decode fields Instruction page Encoding msz 00 PRFB (vector plus immediate) 64-bit element 01 PRFH (vector plus immediate) 64-bit element 10 PRFW (vector plus immediate) 64-bit element 11 PRFD (vector plus immediate) 64-bit element 1 1 0 0 0 1 0 0 0 0 0 1 0 1 Instruction page Encoding LD1Q 1 1 0 0 0 1 0 0 1 1 Decode fields Instruction page Encoding msz U ff 00 0 0 LD1SB (vector plus immediate) 64-bit element 00 0 1 LDFF1SB (vector plus immediate) 64-bit element 00 1 0 LD1B (vector plus immediate) 64-bit element 00 1 1 LDFF1B (vector plus immediate) 64-bit element 01 0 0 LD1SH (vector plus immediate) 64-bit element 01 0 1 LDFF1SH (vector plus immediate) 64-bit element 01 1 0 LD1H (vector plus immediate) 64-bit element 01 1 1 LDFF1H (vector plus immediate) 64-bit element 10 0 0 LD1SW (vector plus immediate) 10 0 1 LDFF1SW (vector plus immediate) 10 1 0 LD1W (vector plus immediate) 64-bit element 10 1 1 LDFF1W (vector plus immediate) 64-bit element 11 0 UNALLOCATED 11 1 0 LD1D (vector plus immediate) 11 1 1 LDFF1D (vector plus immediate) 1 1 0 0 0 1 0 1 0 1 Decode fields Instruction page Encoding msz U ff 00 0 0 LD1SB (scalar plus vector) 64-bit unscaled offset 00 0 1 LDFF1SB (scalar plus vector) 64-bit unscaled offset 00 1 0 LD1B (scalar plus vector) 64-bit unscaled offset 00 1 1 LDFF1B (scalar plus vector) 64-bit unscaled offset 01 0 0 LD1SH (scalar plus vector) 64-bit unscaled offset 01 0 1 LDFF1SH (scalar plus vector) 64-bit unscaled offset 01 1 0 LD1H (scalar plus vector) 64-bit unscaled offset 01 1 1 LDFF1H (scalar plus vector) 64-bit unscaled offset 10 0 0 LD1SW (scalar plus vector) 64-bit unscaled offset 10 0 1 LDFF1SW (scalar plus vector) 64-bit unscaled offset 10 1 0 LD1W (scalar plus vector) 64-bit unscaled offset 10 1 1 LDFF1W (scalar plus vector) 64-bit unscaled offset 11 0 UNALLOCATED 11 1 0 LD1D (scalar plus vector) 64-bit unscaled offset 11 1 1 LDFF1D (scalar plus vector) 64-bit unscaled offset 1 1 0 0 0 1 0 0 0 1 1 1 0 Decode fields Instruction page Encoding msz 00 PRFB (scalar plus vector) 64-bit scaled offset 01 PRFH (scalar plus vector) 64-bit scaled offset 10 PRFW (scalar plus vector) 64-bit scaled offset 11 PRFD (scalar plus vector) 64-bit scaled offset 1 1 0 0 0 1 0 != 00 1 1 1 Decode fields Instruction page Encoding opc U ff 01 0 0 LD1SH (scalar plus vector) 64-bit scaled offset 01 0 1 LDFF1SH (scalar plus vector) 64-bit scaled offset 01 1 0 LD1H (scalar plus vector) 64-bit scaled offset 01 1 1 LDFF1H (scalar plus vector) 64-bit scaled offset 10 0 0 LD1SW (scalar plus vector) 64-bit scaled offset 10 0 1 LDFF1SW (scalar plus vector) 64-bit scaled offset 10 1 0 LD1W (scalar plus vector) 64-bit scaled offset 10 1 1 LDFF1W (scalar plus vector) 64-bit scaled offset 11 0 UNALLOCATED 11 1 0 LD1D (scalar plus vector) 64-bit scaled offset 11 1 1 LDFF1D (scalar plus vector) 64-bit scaled offset 1 0 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding msz ssz Rm 0x 11111 UNALLOCATED 1x UNALLOCATED 00 00 != 11111 LD1RQB (scalar plus scalar) 00 01 != 11111 LD1ROB (scalar plus scalar) 01 00 != 11111 LD1RQH (scalar plus scalar) 01 01 != 11111 LD1ROH (scalar plus scalar) 10 00 != 11111 LD1RQW (scalar plus scalar) 10 01 != 11111 LD1ROW (scalar plus scalar) 11 00 != 11111 LD1RQD (scalar plus scalar) 11 01 != 11111 LD1ROD (scalar plus scalar) 1 0 1 0 0 1 0 0 0 0 1 Decode fields Instruction page Encoding msz ssz 1x UNALLOCATED 00 00 LD1RQB (scalar plus immediate) 00 01 LD1ROB (scalar plus immediate) 01 00 LD1RQH (scalar plus immediate) 01 01 LD1ROH (scalar plus immediate) 10 00 LD1RQW (scalar plus immediate) 10 01 LD1ROW (scalar plus immediate) 11 00 LD1RQD (scalar plus immediate) 11 01 LD1ROD (scalar plus immediate) 1 0 1 0 0 1 0 0 0 1 0 0 1 Decode fields Instruction page Encoding dtype 0x UNALLOCATED 10 LD1W (scalar plus immediate, single register) 128-bit element 11 LD1D (scalar plus immediate, single register) SVE2 1 0 1 0 0 1 0 0 1 0 Decode fields Instruction page Encoding dtype Rm 11111 UNALLOCATED 0000 != 11111 LD1B (scalar plus scalar, single register) 8-bit element 0001 != 11111 LD1B (scalar plus scalar, single register) 16-bit element 0010 != 11111 LD1B (scalar plus scalar, single register) 32-bit element 0011 != 11111 LD1B (scalar plus scalar, single register) 64-bit element 0100 != 11111 LD1SW (scalar plus scalar) 0101 != 11111 LD1H (scalar plus scalar, single register) 16-bit element 0110 != 11111 LD1H (scalar plus scalar, single register) 32-bit element 0111 != 11111 LD1H (scalar plus scalar, single register) 64-bit element 1000 != 11111 LD1SH (scalar plus scalar) 64-bit element 1001 != 11111 LD1SH (scalar plus scalar) 32-bit element 1010 != 11111 LD1W (scalar plus scalar, single register) 32-bit element 1011 != 11111 LD1W (scalar plus scalar, single register) 64-bit element 1100 != 11111 LD1SB (scalar plus scalar) 64-bit element 1101 != 11111 LD1SB (scalar plus scalar) 32-bit element 1110 != 11111 LD1SB (scalar plus scalar) 16-bit element 1111 != 11111 LD1D (scalar plus scalar, single register) SVE 1 0 1 0 0 1 0 0 1 1 Decode fields Instruction page Encoding dtype 0000 LDFF1B (scalar plus scalar) 8-bit element 0001 LDFF1B (scalar plus scalar) 16-bit element 0010 LDFF1B (scalar plus scalar) 32-bit element 0011 LDFF1B (scalar plus scalar) 64-bit element 0100 LDFF1SW (scalar plus scalar) 0101 LDFF1H (scalar plus scalar) 16-bit element 0110 LDFF1H (scalar plus scalar) 32-bit element 0111 LDFF1H (scalar plus scalar) 64-bit element 1000 LDFF1SH (scalar plus scalar) 64-bit element 1001 LDFF1SH (scalar plus scalar) 32-bit element 1010 LDFF1W (scalar plus scalar) 32-bit element 1011 LDFF1W (scalar plus scalar) 64-bit element 1100 LDFF1SB (scalar plus scalar) 64-bit element 1101 LDFF1SB (scalar plus scalar) 32-bit element 1110 LDFF1SB (scalar plus scalar) 16-bit element 1111 LDFF1D (scalar plus scalar) 1 0 1 0 0 1 0 0 0 1 0 0 Decode fields Instruction page Encoding dtype Rm 0x UNALLOCATED 1x 11111 UNALLOCATED 10 != 11111 LD1W (scalar plus scalar, single register) 128-bit element 11 != 11111 LD1D (scalar plus scalar, single register) SVE2 1 0 1 0 0 1 0 0 1 1 0 0 Decode fields Instruction page Encoding num Rm 00 UNALLOCATED 01 != 11111 LD2Q (scalar plus scalar) 10 != 11111 LD3Q (scalar plus scalar) 11 != 11111 LD4Q (scalar plus scalar) != 00 11111 UNALLOCATED 1 0 1 0 0 1 0 0 1 0 1 Decode fields Instruction page Encoding dtype 0000 LD1B (scalar plus immediate, single register) 8-bit element 0001 LD1B (scalar plus immediate, single register) 16-bit element 0010 LD1B (scalar plus immediate, single register) 32-bit element 0011 LD1B (scalar plus immediate, single register) 64-bit element 0100 LD1SW (scalar plus immediate) 0101 LD1H (scalar plus immediate, single register) 16-bit element 0110 LD1H (scalar plus immediate, single register) 32-bit element 0111 LD1H (scalar plus immediate, single register) 64-bit element 1000 LD1SH (scalar plus immediate) 64-bit element 1001 LD1SH (scalar plus immediate) 32-bit element 1010 LD1W (scalar plus immediate, single register) 32-bit element 1011 LD1W (scalar plus immediate, single register) 64-bit element 1100 LD1SB (scalar plus immediate) 64-bit element 1101 LD1SB (scalar plus immediate) 32-bit element 1110 LD1SB (scalar plus immediate) 16-bit element 1111 LD1D (scalar plus immediate, single register) SVE 1 0 1 0 0 1 0 1 1 0 1 Decode fields Instruction page Encoding dtype 0000 LDNF1B 8-bit element 0001 LDNF1B 16-bit element 0010 LDNF1B 32-bit element 0011 LDNF1B 64-bit element 0100 LDNF1SW 0101 LDNF1H 16-bit element 0110 LDNF1H 32-bit element 0111 LDNF1H 64-bit element 1000 LDNF1SH 64-bit element 1001 LDNF1SH 32-bit element 1010 LDNF1W 32-bit element 1011 LDNF1W 64-bit element 1100 LDNF1SB 64-bit element 1101 LDNF1SB 32-bit element 1110 LDNF1SB 16-bit element 1111 LDNF1D 1 0 1 0 0 1 0 0 0 1 1 0 Decode fields Instruction page Encoding msz Rm 11111 UNALLOCATED 00 != 11111 LDNT1B (scalar plus scalar, single register) 01 != 11111 LDNT1H (scalar plus scalar, single register) 10 != 11111 LDNT1W (scalar plus scalar, single register) 11 != 11111 LDNT1D (scalar plus scalar, single register) 1 0 1 0 0 1 0 != 00 1 1 0 Decode fields Instruction page Encoding msz opc Rm != 00 11111 UNALLOCATED 00 01 != 11111 LD2B (scalar plus scalar) 00 10 != 11111 LD3B (scalar plus scalar) 00 11 != 11111 LD4B (scalar plus scalar) 01 01 != 11111 LD2H (scalar plus scalar) 01 10 != 11111 LD3H (scalar plus scalar) 01 11 != 11111 LD4H (scalar plus scalar) 10 01 != 11111 LD2W (scalar plus scalar) 10 10 != 11111 LD3W (scalar plus scalar) 10 11 != 11111 LD4W (scalar plus scalar) 11 01 != 11111 LD2D (scalar plus scalar) 11 10 != 11111 LD3D (scalar plus scalar) 11 11 != 11111 LD4D (scalar plus scalar) 1 0 1 0 0 1 0 0 0 0 1 1 1 Decode fields Instruction page Encoding msz 00 LDNT1B (scalar plus immediate, single register) 01 LDNT1H (scalar plus immediate, single register) 10 LDNT1W (scalar plus immediate, single register) 11 LDNT1D (scalar plus immediate, single register) 1 0 1 0 0 1 0 != 00 0 1 1 1 Decode fields Instruction page Encoding msz opc 00 01 LD2B (scalar plus immediate) 00 10 LD3B (scalar plus immediate) 00 11 LD4B (scalar plus immediate) 01 01 LD2H (scalar plus immediate) 01 10 LD3H (scalar plus immediate) 01 11 LD4H (scalar plus immediate) 10 01 LD2W (scalar plus immediate) 10 10 LD3W (scalar plus immediate) 10 11 LD4W (scalar plus immediate) 11 01 LD2D (scalar plus immediate) 11 10 LD3D (scalar plus immediate) 11 11 LD4D (scalar plus immediate) 1 0 1 0 0 1 0 0 0 1 1 1 1 Decode fields Instruction page Encoding num 00 UNALLOCATED 01 LD2Q (scalar plus immediate) 10 LD3Q (scalar plus immediate) 11 LD4Q (scalar plus immediate) 1 1 1 0 0 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding num 00 UNALLOCATED 01 ST2Q (scalar plus immediate) 10 ST3Q (scalar plus immediate) 11 ST4Q (scalar plus immediate) 1 1 1 0 0 1 0 0 1 0 0 0 Decode fields Instruction page Encoding num Rm 00 UNALLOCATED 01 != 11111 ST2Q (scalar plus scalar) 10 != 11111 ST3Q (scalar plus scalar) 11 != 11111 ST4Q (scalar plus scalar) != 00 11111 UNALLOCATED 1 1 1 0 0 1 0 1 1 0 0 0 0 0 Instruction page Encoding STR (predicate) 1 1 1 0 0 1 0 != 110 0 1 0 Decode fields Instruction page Encoding opc o2 Rm xx1 11111 UNALLOCATED 0x0 11111 UNALLOCATED 00x != 11111 ST1B (scalar plus scalar, single register) 01x != 11111 ST1H (scalar plus scalar, single register) 100 0 11111 UNALLOCATED 100 0 != 11111 ST1W (scalar plus scalar, single register) SVE2 100 1 UNALLOCATED 101 != 11111 ST1W (scalar plus scalar, single register) SVE 111 0 != 11111 ST1D (scalar plus scalar, single register) SVE2 111 1 != 11111 ST1D (scalar plus scalar, single register) SVE 1 1 1 0 0 1 0 1 1 0 0 1 0 Instruction page Encoding STR (vector) 1 1 1 0 0 1 0 0 1 1 1 Decode fields Instruction page Encoding msz opc 00 ST1B (scalar plus immediate, single register) 01 ST1H (scalar plus immediate, single register) 10 00 ST1W (scalar plus immediate, single register) SVE2 10 01 UNALLOCATED 10 1x ST1W (scalar plus immediate, single register) SVE 11 0x UNALLOCATED 11 10 ST1D (scalar plus immediate, single register) SVE2 11 11 ST1D (scalar plus immediate, single register) SVE 1 1 1 0 0 1 0 0 0 1 1 1 1 Decode fields Instruction page Encoding msz 00 STNT1B (scalar plus immediate, single register) 01 STNT1H (scalar plus immediate, single register) 10 STNT1W (scalar plus immediate, single register) 11 STNT1D (scalar plus immediate, single register) 1 1 1 0 0 1 0 != 00 1 1 1 1 Decode fields Instruction page Encoding msz opc 00 01 ST2B (scalar plus immediate) 00 10 ST3B (scalar plus immediate) 00 11 ST4B (scalar plus immediate) 01 01 ST2H (scalar plus immediate) 01 10 ST3H (scalar plus immediate) 01 11 ST4H (scalar plus immediate) 10 01 ST2W (scalar plus immediate) 10 10 ST3W (scalar plus immediate) 10 11 ST4W (scalar plus immediate) 11 01 ST2D (scalar plus immediate) 11 10 ST3D (scalar plus immediate) 11 11 ST4D (scalar plus immediate) 1 1 1 0 0 1 0 0 0 0 1 1 Decode fields Instruction page Encoding msz Rm 11111 UNALLOCATED 00 != 11111 STNT1B (scalar plus scalar, single register) 01 != 11111 STNT1H (scalar plus scalar, single register) 10 != 11111 STNT1W (scalar plus scalar, single register) 11 != 11111 STNT1D (scalar plus scalar, single register) 1 1 1 0 0 1 0 != 00 0 1 1 Decode fields Instruction page Encoding msz opc Rm != 00 11111 UNALLOCATED 00 01 != 11111 ST2B (scalar plus scalar) 00 10 != 11111 ST3B (scalar plus scalar) 00 11 != 11111 ST4B (scalar plus scalar) 01 01 != 11111 ST2H (scalar plus scalar) 01 10 != 11111 ST3H (scalar plus scalar) 01 11 != 11111 ST4H (scalar plus scalar) 10 01 != 11111 ST2W (scalar plus scalar) 10 10 != 11111 ST3W (scalar plus scalar) 10 11 != 11111 ST4W (scalar plus scalar) 11 01 != 11111 ST2D (scalar plus scalar) 11 10 != 11111 ST3D (scalar plus scalar) 11 11 != 11111 ST4D (scalar plus scalar) 1 1 1 0 0 1 0 0 0 0 0 1 Decode fields Instruction page Encoding msz 00 STNT1B (vector plus scalar) 64-bit unscaled offset 01 STNT1H (vector plus scalar) 64-bit unscaled offset 10 STNT1W (vector plus scalar) 64-bit unscaled offset 11 STNT1D (vector plus scalar) 1 1 1 0 0 1 0 1 0 0 0 1 Decode fields Instruction page Encoding msz 00 STNT1B (vector plus scalar) 32-bit unscaled offset 01 STNT1H (vector plus scalar) 32-bit unscaled offset 10 STNT1W (vector plus scalar) 32-bit unscaled offset 11 UNALLOCATED 1 1 1 0 0 1 0 0 0 0 1 0 0 1 Instruction page Encoding ST1Q 1 1 1 0 0 1 0 0 0 1 0 1 Decode fields Instruction page Encoding msz 00 ST1B (scalar plus vector) 64-bit unscaled offset 01 ST1H (scalar plus vector) 64-bit unscaled offset 10 ST1W (scalar plus vector) 64-bit unscaled offset 11 ST1D (scalar plus vector) 64-bit unscaled offset 1 1 1 0 0 1 0 0 1 1 0 1 Decode fields Instruction page Encoding msz 00 UNALLOCATED 01 ST1H (scalar plus vector) 64-bit scaled offset 10 ST1W (scalar plus vector) 64-bit scaled offset 11 ST1D (scalar plus vector) 64-bit scaled offset 1 1 1 0 0 1 0 1 0 1 0 1 Decode fields Instruction page Encoding msz 00 ST1B (vector plus immediate) 64-bit element 01 ST1H (vector plus immediate) 64-bit element 10 ST1W (vector plus immediate) 64-bit element 11 ST1D (vector plus immediate) 1 1 1 0 0 1 0 1 1 1 0 1 Decode fields Instruction page Encoding msz 00 ST1B (vector plus immediate) 32-bit element 01 ST1H (vector plus immediate) 32-bit element 10 ST1W (vector plus immediate) 32-bit element 11 UNALLOCATED 1 1 1 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding msz 00 ST1B (scalar plus vector) 32-bit unpacked unscaled offset 01 ST1H (scalar plus vector) 32-bit unpacked unscaled offset 10 ST1W (scalar plus vector) 32-bit unpacked unscaled offset 11 ST1D (scalar plus vector) 32-bit unpacked unscaled offset 1 1 1 0 0 1 0 1 0 1 0 Decode fields Instruction page Encoding msz 00 ST1B (scalar plus vector) 32-bit unscaled offset 01 ST1H (scalar plus vector) 32-bit unscaled offset 10 ST1W (scalar plus vector) 32-bit unscaled offset 11 UNALLOCATED 1 1 1 0 0 1 0 0 1 1 0 Decode fields Instruction page Encoding msz 00 UNALLOCATED 01 ST1H (scalar plus vector) 32-bit unpacked scaled offset 10 ST1W (scalar plus vector) 32-bit unpacked scaled offset 11 ST1D (scalar plus vector) 32-bit unpacked scaled offset 1 1 1 0 0 1 0 1 1 1 0 Decode fields Instruction page Encoding msz 00 UNALLOCATED 01 ST1H (scalar plus vector) 32-bit scaled offset 10 ST1W (scalar plus vector) 32-bit scaled offset 11 UNALLOCATED 0 1 0 0 0 1 0 1 0 1 0 0 0 Decode fields Instruction page Encoding S tb 0 0 SADDLBT 0 1 UNALLOCATED 1 0 SSUBLBT 1 1 SSUBLTB 0 1 0 0 0 1 0 1 0 1 0 0 1 0 Decode fields Instruction page Encoding tb 0 EORBT 1 EORTB 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 Decode fields Instruction page Encoding uns 00 SMMLA 01 UNALLOCATED 10 USMMLA 11 UMMLA 0 1 0 0 0 1 0 1 0 0 1 0 1 0 Decode fields Instruction page Encoding U T 0 0 SSHLLB 0 1 SSHLLT 1 0 USHLLB 1 1 USHLLT 0 1 0 0 0 1 0 1 0 1 0 1 1 Decode fields Instruction page Encoding opc 00 BEXT 01 BDEP 10 BGRP 11 UNALLOCATED 0 1 0 0 0 1 0 0 1 0 0 0 0 0 Decode fields Instruction page Encoding size U 0x UNALLOCATED 10 0 SDOT (4-way, indexed) 8-bit to 32-bit 10 1 UDOT (4-way, indexed) 8-bit to 32-bit 11 0 SDOT (4-way, indexed) 16-bit to 64-bit 11 1 UDOT (4-way, indexed) 16-bit to 64-bit 0 1 0 0 0 1 0 0 1 0 0 0 0 1 Decode fields Instruction page Encoding size S 0x 0 MLA (indexed) 16-bit 0x 1 MLS (indexed) 16-bit 10 0 MLA (indexed) 32-bit 10 1 MLS (indexed) 32-bit 11 0 MLA (indexed) 64-bit 11 1 MLS (indexed) 64-bit 0 1 0 0 0 1 0 0 1 0 0 0 1 0 Decode fields Instruction page Encoding size S 0x 0 SQRDMLAH (indexed) 16-bit 0x 1 SQRDMLSH (indexed) 16-bit 10 0 SQRDMLAH (indexed) 32-bit 10 1 SQRDMLSH (indexed) 32-bit 11 0 SQRDMLAH (indexed) 64-bit 11 1 SQRDMLSH (indexed) 64-bit 0 1 0 0 0 1 0 0 1 0 0 0 1 1 Decode fields Instruction page Encoding size U 10 0 USDOT (indexed) 10 1 SUDOT != 10 UNALLOCATED 0 1 0 0 0 1 0 0 1 0 0 1 Decode fields Instruction page Encoding size S T 0x UNALLOCATED 10 0 0 SQDMLALB (indexed) 32-bit 10 0 1 SQDMLALT (indexed) 32-bit 10 1 0 SQDMLSLB (indexed) 32-bit 10 1 1 SQDMLSLT (indexed) 32-bit 11 0 0 SQDMLALB (indexed) 64-bit 11 0 1 SQDMLALT (indexed) 64-bit 11 1 0 SQDMLSLB (indexed) 64-bit 11 1 1 SQDMLSLT (indexed) 64-bit 0 1 0 0 0 1 0 0 1 0 1 0 0 Decode fields Instruction page Encoding size 0x UNALLOCATED 10 CDOT (indexed) 8-bit to 32-bit 11 CDOT (indexed) 16-bit to 64-bit 0 1 0 0 0 1 0 0 1 0 1 1 0 Decode fields Instruction page Encoding size 0x UNALLOCATED 10 CMLA (indexed) 16-bit 11 CMLA (indexed) 32-bit 0 1 0 0 0 1 0 0 1 0 1 1 1 Decode fields Instruction page Encoding size 0x UNALLOCATED 10 SQRDCMLAH (indexed) 16-bit 11 SQRDCMLAH (indexed) 32-bit 0 1 0 0 0 1 0 0 1 1 0 Decode fields Instruction page Encoding size S U T 0x UNALLOCATED 10 0 0 0 SMLALB (indexed) 32-bit 10 0 0 1 SMLALT (indexed) 32-bit 10 0 1 0 UMLALB (indexed) 32-bit 10 0 1 1 UMLALT (indexed) 32-bit 10 1 0 0 SMLSLB (indexed) 32-bit 10 1 0 1 SMLSLT (indexed) 32-bit 10 1 1 0 UMLSLB (indexed) 32-bit 10 1 1 1 UMLSLT (indexed) 32-bit 11 0 0 0 SMLALB (indexed) 64-bit 11 0 0 1 SMLALT (indexed) 64-bit 11 0 1 0 UMLALB (indexed) 64-bit 11 0 1 1 UMLALT (indexed) 64-bit 11 1 0 0 SMLSLB (indexed) 64-bit 11 1 0 1 SMLSLT (indexed) 64-bit 11 1 1 0 UMLSLB (indexed) 64-bit 11 1 1 1 UMLSLT (indexed) 64-bit 0 1 0 0 0 1 0 0 1 1 1 0 Decode fields Instruction page Encoding size U T 0x UNALLOCATED 10 0 0 SMULLB (indexed) 32-bit 10 0 1 SMULLT (indexed) 32-bit 10 1 0 UMULLB (indexed) 32-bit 10 1 1 UMULLT (indexed) 32-bit 11 0 0 SMULLB (indexed) 64-bit 11 0 1 SMULLT (indexed) 64-bit 11 1 0 UMULLB (indexed) 64-bit 11 1 1 UMULLT (indexed) 64-bit 0 1 0 0 0 1 0 0 1 1 1 1 0 Decode fields Instruction page Encoding size T 0x UNALLOCATED 10 0 SQDMULLB (indexed) 32-bit 10 1 SQDMULLT (indexed) 32-bit 11 0 SQDMULLB (indexed) 64-bit 11 1 SQDMULLT (indexed) 64-bit 0 1 0 0 0 1 0 0 1 1 1 1 1 0 Decode fields Instruction page Encoding size R 0x 0 SQDMULH (indexed) 16-bit 0x 1 SQRDMULH (indexed) 16-bit 10 0 SQDMULH (indexed) 32-bit 10 1 SQRDMULH (indexed) 32-bit 11 0 SQDMULH (indexed) 64-bit 11 1 SQRDMULH (indexed) 64-bit 0 1 0 0 0 1 0 0 1 1 1 1 1 1 0 Decode fields Instruction page Encoding size 0x MUL (indexed) 16-bit 10 MUL (indexed) 32-bit 11 MUL (indexed) 64-bit 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 Decode fields Instruction page Encoding B S M 1 1 UNALLOCATED 0 0 BRKA 0 1 0 BRKAS 1 0 BRKB 1 1 0 BRKBS 0 0 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 Decode fields Instruction page Encoding S 0 BRKN 1 BRKNS 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 Decode fields Instruction page Encoding opc H 00 0 ZIP1, ZIP2 (predicates) Low halves 00 1 ZIP1, ZIP2 (predicates) High halves 01 0 UZP1, UZP2 (predicates) Even 01 1 UZP1, UZP2 (predicates) Odd 10 0 TRN1, TRN2 (predicates) Even 10 1 TRN1, TRN2 (predicates) Odd 11 UNALLOCATED 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 Decode fields Instruction page Encoding H 0 PUNPKHI, PUNPKLO Low half 1 PUNPKHI, PUNPKLO High half 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 Instruction page Encoding REV (predicate) 0 0 0 0 0 1 0 1 0 0 1 0 0 0 Instruction page Encoding EXT Destructive 0 0 0 0 0 1 0 1 0 1 1 0 0 0 Instruction page Encoding EXT Constructive 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 Instruction page Encoding DUP (indexed) 0 0 0 0 0 1 0 1 1 0 1 1 Decode fields Instruction page Encoding opc 000 ZIP1, ZIP2 (vectors) Low halves 001 ZIP1, ZIP2 (vectors) High halves 010 UZP1, UZP2 (vectors) Even 011 UZP1, UZP2 (vectors) Odd 100 TRN1, TRN2 (vectors) Even 101 TRN1, TRN2 (vectors) Odd 11x UNALLOCATED 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 Instruction page Encoding DUPQ 0 0 0 0 0 1 0 1 0 1 1 0 0 0 1 0 0 1 Instruction page Encoding EXTQ 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 Instruction page Encoding CPY (SIMD&FP scalar) 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 Decode fields Instruction page Encoding size 0x COMPACT Byte and halfword 1x COMPACT Word and doubleword 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 Decode fields Instruction page Encoding B 0 LASTA (SIMD&FP scalar) 1 LASTB (SIMD&FP scalar) 0 0 0 0 0 1 0 1 1 0 0 1 1 0 Decode fields Instruction page Encoding opc Z 00 0 REVB, REVH, REVW Byte, merging 00 1 REVB, REVH, REVW Byte, zeroing 01 0 REVB, REVH, REVW Halfword, merging 01 1 REVB, REVH, REVW Halfword, zeroing 10 0 REVB, REVH, REVW Word, merging 10 1 REVB, REVH, REVW Word, zeroing 11 0 RBIT Merging 11 1 RBIT Zeroing 0 0 0 0 0 1 0 1 1 0 1 0 0 1 0 0 Decode fields Instruction page Encoding B 0 CLASTA (vectors) 1 CLASTB (vectors) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 Decode fields Instruction page Encoding B 0 CLASTA (SIMD&FP scalar) 1 CLASTB (SIMD&FP scalar) 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 Instruction page Encoding SPLICE Destructive 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 Instruction page Encoding SPLICE Constructive 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 1 Decode fields Instruction page Encoding B 0 LASTA (scalar) 1 LASTB (scalar) 0 0 0 0 0 1 0 1 1 0 1 0 0 0 1 0 1 Instruction page Encoding CPY (scalar) 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 Decode fields Instruction page Encoding B 0 CLASTA (scalar) 1 CLASTB (scalar) 0 0 0 0 0 1 0 1 1 0 1 1 1 0 1 0 Decode fields Instruction page Encoding size Z 00 0 REVD Merging 00 1 REVD Zeroing != 00 UNALLOCATED 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 Instruction page Encoding EXPAND 0 0 0 0 0 1 0 1 1 0 1 0 0 0 Decode fields Instruction page Encoding opc H 00 0 ZIP1, ZIP2 (vectors) Low halves (quadwords) 00 1 ZIP1, ZIP2 (vectors) High halves (quadwords) 01 0 UZP1, UZP2 (vectors) Even (quadwords) 01 1 UZP1, UZP2 (vectors) Odd (quadwords) 10 UNALLOCATED 11 0 TRN1, TRN2 (vectors) Even (quadwords) 11 1 TRN1, TRN2 (vectors) Odd (quadwords) 0 0 0 0 0 1 0 1 1 0 0 1 1 0 1 Instruction page Encoding TBXQ 0 0 0 0 0 1 0 1 1 0 0 1 0 1 Decode fields Instruction page Encoding op 0 TBL Two register table 1 TBX 0 1 0 0 0 1 0 0 0 1 1 1 Decode fields Instruction page Encoding opc 000 ZIPQ1 001 ZIPQ2 010 UZPQ1 011 UZPQ2 10x UNALLOCATED 110 TBLQ 111 UNALLOCATED 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 Instruction page Encoding TBL Single register table 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 Instruction page Encoding DUP (scalar) 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 1 1 0 Instruction page Encoding INSR (scalar) 0 0 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 0 0 Decode fields Instruction page Encoding opc opc2 00 00 UNALLOCATED 00 01 PMOV (to predicate) Byte 00 1x PMOV (to predicate) Halfword 01 PMOV (to predicate) Word 1x PMOV (to predicate) Doubleword 0 0 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 Decode fields Instruction page Encoding opc opc2 00 00 UNALLOCATED 00 01 PMOV (to vector) Byte 00 1x PMOV (to vector) Halfword 01 PMOV (to vector) Word 1x PMOV (to vector) Doubleword 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 0 Decode fields Instruction page Encoding U H 0 0 SUNPKHI, SUNPKLO Low half 0 1 SUNPKHI, SUNPKLO High half 1 0 UUNPKHI, UUNPKLO Low half 1 1 UUNPKHI, UUNPKLO High half 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 1 1 0 Instruction page Encoding INSR (SIMD&FP scalar) 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0 Instruction page Encoding REV (vector) 0 0 1 0 0 1 0 1 1 0 0 1 0 0 Decode fields Instruction page Encoding opc 000 CNTP (predicate) 001 FIRSTP 010 LASTP 011 UNALLOCATED 1xx UNALLOCATED 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 1 Decode fields Instruction page Encoding opc 000 CNTP (predicate as counter) != 000 UNALLOCATED 0 0 1 0 0 1 0 1 0 0 0 1 Decode fields Instruction page Encoding op S o2 o3 0 0 0 0 AND (predicates) 0 0 0 1 BIC (predicates) 0 0 1 0 EOR (predicates) 0 0 1 1 SEL (predicates) 0 1 0 0 ANDS 0 1 0 1 BICS 0 1 1 0 EORS 0 1 1 1 UNALLOCATED 1 0 0 0 ORR (predicates) 1 0 0 1 ORN (predicates) 1 0 1 0 NOR 1 0 1 1 NAND 1 1 0 0 ORRS 1 1 0 1 ORNS 1 1 1 0 NORS 1 1 1 1 NANDS 0 0 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 Decode fields Instruction page Encoding op S opc2 0 0 UNALLOCATED 0 1 0000 PTEST 0 1 != 0000 UNALLOCATED 1 UNALLOCATED 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op S 0 0 UNALLOCATED 0 1 PFIRST 1 UNALLOCATED 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 Instruction page Encoding PNEXT 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding S 0 PTRUE (predicate) 1 PTRUES 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 Decode fields Instruction page Encoding op S 0 0 PFALSE 0 1 UNALLOCATED 1 UNALLOCATED 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 0 Decode fields Instruction page Encoding op S 0 0 RDFFR (predicated) 0 1 RDFFRS 1 UNALLOCATED 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding op S 0 0 RDFFR (unpredicated) 0 1 UNALLOCATED 1 UNALLOCATED 0 0 1 0 0 1 0 1 1 0 1 0 Decode fields Instruction page Encoding S 0 PSEL 1 UNALLOCATED 0 0 1 0 0 1 0 1 0 0 1 1 0 Decode fields Instruction page Encoding op S B 0 0 0 BRKPA 0 0 1 BRKPB 0 1 0 BRKPAS 0 1 1 BRKPBS 1 UNALLOCATED 0 0 1 0 0 1 0 1 1 0 1 0 1 Decode fields Instruction page Encoding U lt eq 0 0 0 WHILEGE (predicate as counter) 0 0 1 WHILEGT (predicate as counter) 0 1 0 WHILELT (predicate as counter) 0 1 1 WHILELE (predicate as counter) 1 0 0 WHILEHS (predicate as counter) 1 0 1 WHILEHI (predicate as counter) 1 1 0 WHILELO (predicate as counter) 1 1 1 WHILELS (predicate as counter) 0 0 1 0 0 1 0 1 1 0 1 0 1 1 Decode fields Instruction page Encoding U lt eq 0 0 0 WHILEGE (predicate pair) 0 0 1 WHILEGT (predicate pair) 0 1 0 WHILELT (predicate pair) 0 1 1 WHILELE (predicate pair) 1 0 0 WHILEHS (predicate pair) 1 0 1 WHILEHI (predicate pair) 1 1 0 WHILELO (predicate pair) 1 1 1 WHILELS (predicate pair) 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 Decode fields Instruction page Encoding opc 0xx PEXT (predicate) 10x PEXT (predicate pair) 11x UNALLOCATED 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 Instruction page Encoding PTRUE (predicate as counter) 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 Decode fields Instruction page Encoding op 0 ADDVL 1 ADDPL 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 Decode fields Instruction page Encoding op 0 ADDSVL 1 ADDSPL 0 0 0 0 0 1 0 0 1 1 0 1 0 1 0 Decode fields Instruction page Encoding op opc2 0 11111 RDVL 0 != 11111 UNALLOCATED 1 UNALLOCATED 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 Decode fields Instruction page Encoding op opc2 0 11111 RDSVL 0 != 11111 UNALLOCATED 1 UNALLOCATED 0 0 0 0 0 1 0 1 1 1 1 Instruction page Encoding SEL (vectors) 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding opc 00 WRFFR != 00 UNALLOCATED 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Decode fields Instruction page Encoding opc 00 SETFFR != 00 UNALLOCATED 0 1 1 0 0 1 0 1 0 1 1 0 0 0 1 Decode fields Instruction page Encoding opc 00 FADDA != 00 UNALLOCATED 0 1 1 0 0 1 0 1 0 0 1 0 0 Decode fields Instruction page Encoding size opc 0011 FSUBR (vectors) 1000 FABD 1010 FMULX 1011 UNALLOCATED 1100 FDIVR 1101 FDIV 1110 FAMAX 1111 FAMIN 00 0000 BFADD (predicated) 00 0001 BFSUB (predicated) 00 0010 BFMUL (vectors, predicated) 00 0100 BFMAXNM 00 0101 BFMINNM 00 0110 BFMAX 00 0111 BFMIN 00 1001 BFSCALE != 00 0000 FADD (vectors, predicated) != 00 0001 FSUB (vectors, predicated) != 00 0010 FMUL (vectors, predicated) != 00 0100 FMAXNM (vectors) != 00 0101 FMINNM (vectors) != 00 0110 FMAX (vectors) != 00 0111 FMIN (vectors) != 00 1001 FSCALE 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 Instruction page Encoding FTMAD 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 0 0 Decode fields Instruction page Encoding opc 000 FADD (immediate) 001 FSUB (immediate) 010 FMUL (immediate) 011 FSUBR (immediate) 100 FMAXNM (immediate) 101 FMINNM (immediate) 110 FMAX (immediate) 111 FMIN (immediate) 0 1 1 0 0 1 0 1 0 0 0 0 Decode fields Instruction page Encoding size opc 011 FTSMUL 10x UNALLOCATED 110 FRECPS 111 FRSQRTS 00 000 BFADD (unpredicated) 00 001 BFSUB (unpredicated) 00 010 BFMUL (vectors, unpredicated) != 00 000 FADD (vectors, unpredicated) != 00 001 FSUB (vectors, unpredicated) != 00 010 FMUL (vectors, unpredicated) 0 1 1 0 0 1 0 1 0 1 Decode fields Instruction page Encoding op o2 o3 0 0 0 FCM<cc> (vectors) Greater than or equal 0 0 1 FCM<cc> (vectors) Greater than 0 1 0 FCM<cc> (vectors) Equal 0 1 1 FCM<cc> (vectors) Not equal 1 0 0 FCM<cc> (vectors) Unordered 1 0 1 FAC<cc> Greater than or equal 1 1 0 UNALLOCATED 1 1 1 FAC<cc> Greater than 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 Decode fields Instruction page Encoding eq lt ne 0 0 0 FCM<cc> (zero) Greater than or equal 0 0 1 FCM<cc> (zero) Greater than 0 1 0 FCM<cc> (zero) Less than 0 1 1 FCM<cc> (zero) Less than or equal 1 1 UNALLOCATED 1 0 0 FCM<cc> (zero) Equal 1 1 0 FCM<cc> (zero) Not equal 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 Instruction page Encoding FCADD 0 1 1 0 0 1 0 0 1 0 0 0 1 Decode fields Instruction page Encoding size 0x UNALLOCATED 10 FCMLA (indexed) Half-precision 11 FCMLA (indexed) Single-precision 0 1 1 0 0 1 0 0 0 0 Instruction page Encoding FCMLA (vectors) 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 Decode fields Instruction page Encoding opc opc2 x0 11 UNALLOCATED 00 0x UNALLOCATED 00 10 FCVTXNT Double-precision to single-precision, zeroing 01 UNALLOCATED 10 00 FCVTNT (predicated) Single-precision to half-precision, zeroing 10 01 FCVTLT Half-precision to single-precision, zeroing 10 10 BFCVTNT Zeroing 11 0x UNALLOCATED 11 10 FCVTNT (predicated) Double-precision to single-precision, zeroing 11 11 FCVTLT Single-precision to double-precision, zeroing 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 Decode fields Instruction page Encoding opc opc2 x0 11 UNALLOCATED 00 0x UNALLOCATED 00 10 FCVTXNT Double-precision to single-precision, merging 01 UNALLOCATED 10 00 FCVTNT (predicated) Single-precision to half-precision, merging 10 01 FCVTLT Half-precision to single-precision, merging 10 10 BFCVTNT Merging 11 0x UNALLOCATED 11 10 FCVTNT (predicated) Double-precision to single-precision, merging 11 11 FCVTLT Single-precision to double-precision, merging 0 1 1 0 0 1 0 1 0 0 0 0 0 1 Decode fields Instruction page Encoding opc 000 FADDV 001 UNALLOCATED 01x UNALLOCATED 100 FMAXNMV 101 FMINNMV 110 FMAXV 111 FMINV 0 1 1 0 0 1 0 0 0 1 0 1 0 1 Decode fields Instruction page Encoding opc 000 FADDQV 001 UNALLOCATED 01x UNALLOCATED 100 FMAXNMQV 101 FMINNMQV 110 FMAXQV 111 FMINQV 0 1 1 0 0 1 0 0 1 1 1 1 0 0 1 Decode fields Instruction page Encoding opc 00 FMMLA (widening, FP16 to FP32) 01 BFMMLA (widening) 10 FMMLA (non-widening) 32-bit element 11 FMMLA (non-widening) 64-bit element 0 1 1 0 0 1 0 0 1 0 0 1 0 0 Decode fields Instruction page Encoding size o2 0x 0 FMUL (indexed) Half-precision 0x 1 BFMUL (indexed) 1x 1 UNALLOCATED 10 0 FMUL (indexed) Single-precision 11 0 FMUL (indexed) Double-precision 0 1 1 0 0 1 0 1 1 0 Decode fields Instruction page Encoding size opc 00 00 BFMLA (vectors) 00 01 BFMLS (vectors) 00 1x UNALLOCATED != 00 00 FMLA (vectors) != 00 01 FMLS (vectors) != 00 10 FNMLA != 00 11 FNMLS 0 1 1 0 0 1 0 1 1 1 Decode fields Instruction page Encoding opc 00 FMAD 01 FMSB 10 FNMAD 11 FNMSB 0 1 1 0 0 1 0 0 1 0 0 0 0 Decode fields Instruction page Encoding size o2 op 0x 0 0 FMLA (indexed) Half-precision 0x 0 1 FMLS (indexed) Half-precision 0x 1 0 BFMLA (indexed) 0x 1 1 BFMLS (indexed) 1x 1 UNALLOCATED 10 0 0 FMLA (indexed) Single-precision 10 0 1 FMLS (indexed) Single-precision 11 0 0 FMLA (indexed) Double-precision 11 0 1 FMLS (indexed) Double-precision 0 1 1 0 0 1 0 1 0 0 0 1 0 1 Decode fields Instruction page Encoding opc 000 FRINT<r> Nearest with ties to even, merging 001 FRINT<r> Toward plus infinity, merging 010 FRINT<r> Toward minus infinity, merging 011 FRINT<r> Toward zero, merging 100 FRINT<r> Nearest with ties to away, merging 101 UNALLOCATED 110 FRINT<r> Current mode signalling inexact, merging 111 FRINT<r> Current mode, merging 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 Decode fields Instruction page Encoding opc opc2 x0 11 UNALLOCATED 00 0x UNALLOCATED 00 10 FCVTX Double-precision to single-precision, merging 01 UNALLOCATED 10 00 FCVT Single-precision to half-precision, merging 10 01 FCVT Half-precision to single-precision, merging 10 10 BFCVT Merging 11 00 FCVT Double-precision to half-precision, merging 11 01 FCVT Half-precision to double-precision, merging 11 10 FCVT Double-precision to single-precision, merging 11 11 FCVT Single-precision to double-precision, merging 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 Decode fields Instruction page Encoding opc 00 FRECPX Merging 01 FSQRT Merging 1x UNALLOCATED 0 1 1 0 0 1 0 1 0 1 0 1 0 1 Decode fields Instruction page Encoding opc opc2 U 00 0x 0 FRINT32Z Merging 00 0x 1 FRINT32X Merging 00 1x 0 FRINT64Z Merging 00 1x 1 FRINT64X Merging 01 00 UNALLOCATED 01 01 0 SCVTF (predicated) 16-bit to half-precision, merging 01 01 1 UCVTF (predicated) 16-bit to half-precision, merging 01 10 0 SCVTF (predicated) 32-bit to half-precision, merging 01 10 1 UCVTF (predicated) 32-bit to half-precision, merging 01 11 0 SCVTF (predicated) 64-bit to half-precision, merging 01 11 1 UCVTF (predicated) 64-bit to half-precision, merging 10 10 0 SCVTF (predicated) 32-bit to single-precision, merging 10 10 1 UCVTF (predicated) 32-bit to single-precision, merging 10 != 10 UNALLOCATED 11 00 0 SCVTF (predicated) 32-bit to double-precision, merging 11 00 1 UCVTF (predicated) 32-bit to double-precision, merging 11 01 UNALLOCATED 11 10 0 SCVTF (predicated) 64-bit to single-precision, merging 11 10 1 UCVTF (predicated) 64-bit to single-precision, merging 11 11 0 SCVTF (predicated) 64-bit to double-precision, merging 11 11 1 UCVTF (predicated) 64-bit to double-precision, merging 0 1 1 0 0 1 0 1 0 1 1 1 0 1 Decode fields Instruction page Encoding opc opc2 U 00 0 FLOGB Merging 00 1 UNALLOCATED 01 00 UNALLOCATED 01 01 0 FCVTZS Half-precision to 16-bit, merging 01 01 1 FCVTZU Half-precision to 16-bit, merging 01 10 0 FCVTZS Half-precision to 32-bit, merging 01 10 1 FCVTZU Half-precision to 32-bit, merging 01 11 0 FCVTZS Half-precision to 64-bit, merging 01 11 1 FCVTZU Half-precision to 64-bit, merging 10 10 0 FCVTZS Single-precision to 32-bit, merging 10 10 1 FCVTZU Single-precision to 32-bit, merging 10 != 10 UNALLOCATED 11 00 0 FCVTZS Double-precision to 32-bit, merging 11 00 1 FCVTZU Double-precision to 32-bit, merging 11 01 UNALLOCATED 11 10 0 FCVTZS Single-precision to 64-bit, merging 11 10 1 FCVTZU Single-precision to 64-bit, merging 11 11 0 FCVTZS Double-precision to 64-bit, merging 11 11 1 FCVTZU Double-precision to 64-bit, merging 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 Decode fields Instruction page Encoding L opc 0 00 F1CVT, F2CVT F1CVT 0 01 F1CVT, F2CVT F2CVT 0 10 BF1CVT, BF2CVT BF1CVT 0 11 BF1CVT, BF2CVT BF2CVT 1 00 F1CVTLT, F2CVTLT F1CVTLT 1 01 F1CVTLT, F2CVTLT F2CVTLT 1 10 BF1CVTLT, BF2CVTLT BF1CVTLT 1 11 BF1CVTLT, BF2CVTLT BF2CVTLT 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 1 1 0 Decode fields Instruction page Encoding opc 00 FCVTN 01 FCVTNB 10 BFCVTN 11 FCVTNT (unpredicated) 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 1 0 0 Decode fields Instruction page Encoding op 0 FRECPE 1 FRSQRTE 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 Decode fields Instruction page Encoding op o2 0 0 FDOT (2-way, vectors, FP16 to FP32) 0 1 FDOT (2-way, vectors, FP8 to FP16) 1 0 BFDOT (vectors) 1 1 FDOT (4-way, vectors) 0 1 1 0 0 1 0 0 1 1 1 0 0 0 Decode fields Instruction page Encoding o2 op T 0 0 0 FMLALB (vectors, FP16 to FP32) 0 0 1 FMLALT (vectors, FP16 to FP32) 0 1 0 FMLSLB (vectors) 0 1 1 FMLSLT (vectors) 1 0 0 BFMLALB (vectors) 1 0 1 BFMLALT (vectors) 1 1 0 BFMLSLB (vectors) 1 1 1 BFMLSLT (vectors) 0 1 1 0 0 1 0 0 0 1 0 1 0 0 Decode fields Instruction page Encoding op opc2 0 x1 FDOT (2-way, indexed, FP8 to FP16) 0 00 FDOT (2-way, indexed, FP16 to FP32) 0 10 UNALLOCATED 1 00 BFDOT (indexed) 1 01 FDOT (4-way, indexed) 1 1x UNALLOCATED 0 1 1 0 0 1 0 0 1 1 0 1 0 Decode fields Instruction page Encoding o2 op T 0 0 0 FMLALB (indexed, FP16 to FP32) 0 0 1 FMLALT (indexed, FP16 to FP32) 0 1 0 FMLSLB (indexed) 0 1 1 FMLSLT (indexed) 1 0 0 BFMLALB (indexed) 1 0 1 BFMLALT (indexed) 1 1 0 BFMLSLB (indexed) 1 1 1 BFMLSLT (indexed) 0 1 0 0 0 1 0 0 0 1 1 0 0 0 Decode fields Instruction page Encoding U 0 SCLAMP 1 UCLAMP 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 Decode fields Instruction page Encoding U 0 SDOT (2-way, vectors) 1 UDOT (2-way, vectors) 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 Decode fields Instruction page Encoding U 0 SDOT (2-way, indexed) 1 UDOT (2-way, indexed) 0 1 0 0 0 1 0 1 0 1 1 0 0 Decode fields Instruction page Encoding U T 0 0 SABALB 0 1 SABALT 1 0 UABALB 1 1 UABALT 0 1 0 0 0 1 0 1 0 1 1 0 1 0 Decode fields Instruction page Encoding size T 0x 0 ADCLB 0x 1 ADCLT 1x 0 SBCLB 1x 1 SBCLT 0 1 0 0 0 1 0 1 0 0 0 0 0 1 1 0 1 1 Decode fields Instruction page Encoding op 0 CADD 1 SQCADD 0 1 0 0 0 1 0 1 0 1 1 1 0 Decode fields Instruction page Encoding R U 0 0 SSRA 0 1 USRA 1 0 SRSRA 1 1 URSRA 0 1 0 0 0 1 0 1 0 1 1 1 1 0 Decode fields Instruction page Encoding op 0 SRI 1 SLI 0 1 0 0 0 1 0 1 0 1 1 1 1 1 Decode fields Instruction page Encoding U 0 SABA 1 UABA 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 Decode fields Instruction page Encoding size op 00 0 AESMC 00 1 AESIMC != 00 UNALLOCATED 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 Decode fields Instruction page Encoding size op o2 00 0 0 AESE (vectors) 00 0 1 AESD (vectors) 00 1 0 SM4E 00 1 1 UNALLOCATED != 00 UNALLOCATED 0 1 0 0 0 1 0 1 1 0 1 1 1 1 0 1 Decode fields Instruction page Encoding size op o2 o3 00 1 UNALLOCATED 00 0 0 0 AESE (indexed) Two registers 00 0 1 0 AESD (indexed) Two registers 00 1 0 0 AESEMC Two registers 00 1 1 0 AESDIMC Two registers != 00 UNALLOCATED 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 1 Decode fields Instruction page Encoding size op o2 opc3 00 != 00 UNALLOCATED 00 0 0 00 AESE (indexed) Four registers 00 0 1 00 AESD (indexed) Four registers 00 1 0 00 AESEMC Four registers 00 1 1 00 AESDIMC Four registers != 00 UNALLOCATED 0 1 0 0 0 1 0 1 1 1 1 1 1 0 Decode fields Instruction page Encoding size op 00 0 SM4EKEY 00 1 RAX1 != 00 UNALLOCATED 0 1 0 0 0 1 0 1 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding size 00 PMULL != 00 UNALLOCATED 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding size 00 PMLAL != 00 UNALLOCATED 0 1 1 0 0 1 0 0 0 1 0 1 0 1 Decode fields Instruction page Encoding T 0 FMLALB (indexed, FP8 to FP16) 1 FMLALT (indexed, FP8 to FP16) 0 1 1 0 0 1 0 0 1 1 1 0 0 Decode fields Instruction page Encoding TT 00 FMLALLBB (indexed) 01 FMLALLBT (indexed) 10 FMLALLTB (indexed) 11 FMLALLTT (indexed) 0 1 1 0 0 1 0 0 0 1 1 1 1 0 0 0 Decode fields Instruction page Encoding op 0 FMMLA (widening, FP8 to FP32) 1 FMMLA (widening, FP8 to FP16) 0 1 1 0 0 1 0 0 0 0 1 1 0 1 0 Decode fields Instruction page Encoding TT 00 FMLALLBB (vectors) 01 FMLALLBT (vectors) 10 FMLALLTB (vectors) 11 FMLALLTT (vectors) 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 Decode fields Instruction page Encoding T 0 FMLALB (vectors, FP8 to FP16) 1 FMLALT (vectors, FP8 to FP16) 0 1 0 0 0 1 0 1 1 1 0 1 0 0 0 Instruction page Encoding HISTSEG 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0 Instruction page Encoding LUTI2 (8-bit and 16-bit) Byte 0 1 0 0 0 1 0 1 1 1 0 1 1 0 Instruction page Encoding LUTI2 (8-bit and 16-bit) Halfword 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 1 Instruction page Encoding LUTI4 (8-bit and 16-bit) Byte, single register table 0 1 0 0 0 1 0 1 1 1 0 1 1 1 Decode fields Instruction page Encoding op 0 LUTI4 (8-bit and 16-bit) Halfword, two register table 1 LUTI4 (8-bit and 16-bit) Halfword, single register table 0 1 0 0 0 1 0 0 0 0 1 0 0 Decode fields Instruction page Encoding Q R N U 0 0 UNALLOCATED 0 0 1 0 SRSHL 0 0 1 1 URSHL 0 1 1 0 SRSHLR 0 1 1 1 URSHLR 1 0 0 0 SQSHL (vectors) 1 0 0 1 UQSHL (vectors) 1 0 1 0 SQRSHL 1 0 1 1 UQRSHL 1 1 0 0 SQSHLR 1 1 0 1 UQSHLR 1 1 1 0 SQRSHLR 1 1 1 1 UQRSHLR 0 1 0 0 0 1 0 0 0 0 0 1 0 1 Decode fields Instruction page Encoding Q Z op 0 0 0 URECPE Merging 0 0 1 URSQRTE Merging 0 1 0 URECPE Zeroing 0 1 1 URSQRTE Zeroing 1 0 0 SQABS Merging 1 0 1 SQNEG Merging 1 1 0 SQABS Zeroing 1 1 1 SQNEG Zeroing 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 Decode fields Instruction page Encoding U 0 SADALP 1 UADALP 0 1 0 0 0 1 0 0 0 1 0 1 0 0 Decode fields Instruction page Encoding R S U 0 0 0 SHADD 0 0 1 UHADD 0 1 0 SHSUB 0 1 1 UHSUB 1 0 0 SRHADD 1 0 1 URHADD 1 1 0 SHSUBR 1 1 1 UHSUBR 0 1 0 0 0 1 0 0 0 1 0 1 0 1 Decode fields Instruction page Encoding opc U 00 0 UNALLOCATED 00 1 ADDP 01 UNALLOCATED 10 0 SMAXP 10 1 UMAXP 11 0 SMINP 11 1 UMINP 0 1 0 0 0 1 0 0 0 1 1 1 0 0 Decode fields Instruction page Encoding op S U 0 0 0 SQADD (vectors, predicated) 0 0 1 UQADD (vectors, predicated) 0 1 0 SQSUB (vectors, predicated) 0 1 1 UQSUB (vectors, predicated) 1 0 0 SUQADD 1 0 1 USQADD 1 1 0 SQSUBR 1 1 1 UQSUBR 0 0 0 0 0 1 0 0 1 0 1 1 0 Decode fields Instruction page Encoding size opc 00 MUL (vectors, unpredicated) 10 SMULH (unpredicated) 11 UMULH (unpredicated) 00 01 PMUL != 00 01 UNALLOCATED 0 0 0 0 0 1 0 0 1 0 1 1 1 0 Decode fields Instruction page Encoding R 0 SQDMULH (vectors) 1 SQRDMULH (vectors) 0 1 0 0 0 1 0 1 0 1 0 0 Decode fields Instruction page Encoding op U R T 0 0 0 0 SQSHRUNB 0 0 0 1 SQSHRUNT 0 0 1 0 SQRSHRUNB 0 0 1 1 SQRSHRUNT 0 1 0 0 SHRNB 0 1 0 1 SHRNT 0 1 1 0 RSHRNB 0 1 1 1 RSHRNT 1 0 0 0 SQSHRNB 1 0 0 1 SQSHRNT 1 0 1 0 SQRSHRNB 1 0 1 1 SQRSHRNT 1 1 0 0 UQSHRNB 1 1 0 1 UQSHRNT 1 1 1 0 UQRSHRNB 1 1 1 1 UQRSHRNT 0 1 0 0 0 1 0 1 1 1 0 0 0 0 Decode fields Instruction page Encoding op0 opc op1 U R 0 0xxxx UNALLOCATED 0 1xxxx 0 UNALLOCATED 0 1xxxx 0 0 1 SQRSHRUN 0 1xxxx 0 1 1 UNALLOCATED 0 1xxxx 1 0 1 SQRSHRN 0 1xxxx 1 1 1 UQRSHRN 1 UNALLOCATED 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 Decode fields Instruction page Encoding opc T 00 0 SQXTNB 00 1 SQXTNT 01 0 UQXTNB 01 1 UQXTNT 10 0 SQXTUNB 10 1 SQXTUNT 11 UNALLOCATED 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 Decode fields Instruction page Encoding tszh tszl opc 0 10 00 SQCVTN 0 10 01 UQCVTN 0 10 10 SQCVTUN 0 10 11 UNALLOCATED 0 != 10 UNALLOCATED 1 UNALLOCATED 0 1 0 0 0 1 0 1 1 0 1 1 Decode fields Instruction page Encoding S R T 0 0 0 ADDHNB 0 0 1 ADDHNT 0 1 0 RADDHNB 0 1 1 RADDHNT 1 0 0 SUBHNB 1 0 1 SUBHNT 1 1 0 RSUBHNB 1 1 1 RSUBHNT 0 1 0 0 0 1 0 1 1 1 0 0 Decode fields Instruction page Encoding op 0 MATCH 1 NMATCH 0 1 0 0 0 1 0 1 0 0 0 Decode fields Instruction page Encoding op S U T 0 0 0 0 SADDLB 0 0 0 1 SADDLT 0 0 1 0 UADDLB 0 0 1 1 UADDLT 0 1 0 0 SSUBLB 0 1 0 1 SSUBLT 0 1 1 0 USUBLB 0 1 1 1 USUBLT 1 0 UNALLOCATED 1 1 0 0 SABDLB 1 1 0 1 SABDLT 1 1 1 0 UABDLB 1 1 1 1 UABDLT 0 1 0 0 0 1 0 1 0 0 1 0 Decode fields Instruction page Encoding S U T 0 0 0 SADDWB 0 0 1 SADDWT 0 1 0 UADDWB 0 1 1 UADDWT 1 0 0 SSUBWB 1 0 1 SSUBWT 1 1 0 USUBWB 1 1 1 USUBWT 0 1 0 0 0 1 0 1 0 0 1 1 Decode fields Instruction page Encoding size op U T 0 0 0 SQDMULLB (vectors) 0 0 1 SQDMULLT (vectors) 1 0 0 SMULLB (vectors) 1 0 1 SMULLT (vectors) 1 1 0 UMULLB (vectors) 1 1 1 UMULLT (vectors) 00 0 1 0 PMULLB 128-bit element 00 0 1 1 PMULLT 128-bit element != 00 0 1 0 PMULLB 16-bit or 64-bit elements != 00 0 1 1 PMULLT 16-bit or 64-bit elements 0 1 1 0 0 1 0 0 0 1 0 1 0 0 Decode fields Instruction page Encoding opc 000 FADDP 001 UNALLOCATED 01x UNALLOCATED 100 FMAXNMP 101 FMINNMP 110 FMAXP 111 FMINP 0 1 1 0 0 1 0 0 0 1 1 0 0 1 Decode fields Instruction page Encoding op opc2 0 00 FRINT<r> Nearest with ties to even, zeroing 0 01 FRINT<r> Toward plus infinity, zeroing 0 10 FRINT<r> Toward minus infinity, zeroing 0 11 FRINT<r> Toward zero, zeroing 1 00 FRINT<r> Nearest with ties to away, zeroing 1 01 UNALLOCATED 1 10 FRINT<r> Current mode signalling inexact, zeroing 1 11 FRINT<r> Current mode, zeroing 0 1 1 0 0 1 0 0 0 1 1 0 1 0 1 Decode fields Instruction page Encoding opc opc2 x0 11 UNALLOCATED 00 0x UNALLOCATED 00 10 FCVTX Double-precision to single-precision, zeroing 01 UNALLOCATED 10 00 FCVT Single-precision to half-precision, zeroing 10 01 FCVT Half-precision to single-precision, zeroing 10 10 BFCVT Zeroing 11 00 FCVT Double-precision to half-precision, zeroing 11 01 FCVT Half-precision to double-precision, zeroing 11 10 FCVT Double-precision to single-precision, zeroing 11 11 FCVT Single-precision to double-precision, zeroing 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 Decode fields Instruction page Encoding opc 00 FRECPX Zeroing 01 FSQRT Zeroing 1x UNALLOCATED 0 1 1 0 0 1 0 0 0 1 1 1 0 1 Decode fields Instruction page Encoding opc o2 o3 U 00 0 0 FRINT32Z Zeroing 00 0 1 FRINT32X Zeroing 00 1 0 FRINT64Z Zeroing 00 1 1 FRINT64X Zeroing 01 0 0 UNALLOCATED 01 0 1 0 SCVTF (predicated) 16-bit to half-precision, zeroing 01 0 1 1 UCVTF (predicated) 16-bit to half-precision, zeroing 01 1 0 0 SCVTF (predicated) 32-bit to half-precision, zeroing 01 1 0 1 UCVTF (predicated) 32-bit to half-precision, zeroing 01 1 1 0 SCVTF (predicated) 64-bit to half-precision, zeroing 01 1 1 1 UCVTF (predicated) 64-bit to half-precision, zeroing 10 0 UNALLOCATED 10 1 0 0 SCVTF (predicated) 32-bit to single-precision, zeroing 10 1 0 1 UCVTF (predicated) 32-bit to single-precision, zeroing 10 1 1 UNALLOCATED 11 0 0 0 SCVTF (predicated) 32-bit to double-precision, zeroing 11 0 0 1 UCVTF (predicated) 32-bit to double-precision, zeroing 11 0 1 UNALLOCATED 11 1 0 0 SCVTF (predicated) 64-bit to single-precision, zeroing 11 1 0 1 UCVTF (predicated) 64-bit to single-precision, zeroing 11 1 1 0 SCVTF (predicated) 64-bit to double-precision, zeroing 11 1 1 1 UCVTF (predicated) 64-bit to double-precision, zeroing 0 1 1 0 0 1 0 0 0 1 1 1 1 1 Decode fields Instruction page Encoding opc o2 o3 U 00 0 FLOGB Zeroing 00 1 UNALLOCATED 01 0 0 UNALLOCATED 01 0 1 0 FCVTZS Half-precision to 16-bit, zeroing 01 0 1 1 FCVTZU Half-precision to 16-bit, zeroing 01 1 0 0 FCVTZS Half-precision to 32-bit, zeroing 01 1 0 1 FCVTZU Half-precision to 32-bit, zeroing 01 1 1 0 FCVTZS Half-precision to 64-bit, zeroing 01 1 1 1 FCVTZU Half-precision to 64-bit, zeroing 10 0 UNALLOCATED 10 1 0 0 FCVTZS Single-precision to 32-bit, zeroing 10 1 0 1 FCVTZU Single-precision to 32-bit, zeroing 10 1 1 UNALLOCATED 11 0 0 0 FCVTZS Double-precision to 32-bit, zeroing 11 0 0 1 FCVTZU Double-precision to 32-bit, zeroing 11 0 1 UNALLOCATED 11 1 0 0 FCVTZS Single-precision to 64-bit, zeroing 11 1 0 1 FCVTZU Single-precision to 64-bit, zeroing 11 1 1 0 FCVTZS Double-precision to 64-bit, zeroing 11 1 1 1 FCVTZU Double-precision to 64-bit, zeroing 0 1 0 0 0 1 0 1 1 1 1 0 Instruction page Encoding HISTCNT 0 1 0 0 0 1 0 0 0 1 1 0 1 0 Decode fields Instruction page Encoding opc o2 11 0 MLAPT 11 1 MADPT != 11 UNALLOCATED