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<instructionsection id="ERET" title="ERET -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="system"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="ERET"/>
  </docvars>
  <heading>ERET</heading>
  <desc>
    <brief>
      <para>Exception return</para>
    </brief>
    <authored>
      <para>This instruction restores <xref linkend="ARMARM_PSTATE">PSTATE</xref> from the SPSR, and branches to
the address held in the ELR.</para>
      <para>The SPSR is checked for the current Exception level for an illegal return event.
See <xref linkend="ARMARM_MDSec.illegal_exception_returns_from_aarch64_state">Illegal exception returns from AArch64 state</xref>.</para>
      <para><instruction>ERET</instruction> is <arm-defined-word>UNDEFINED</arm-defined-word> at EL0.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="system"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="ERET"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A64.control.branch_reg.ERET_64E_branch_reg" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" width="4" name="opc" usename="1" settings="4" psbits="xxxx">
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="op2" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" name="A" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="10" name="M" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="4" width="5" name="op4" usename="1" settings="5" psbits="xxxxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="ERET_64E_branch_reg" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="system"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="ERET"/>
        </docvars>
        <asmtemplate><text>ERET</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.control.branch_reg.ERET_64E_branch_reg" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let pac : boolean = FALSE;
let use_key_a : boolean = TRUE;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"/>
  <ps_section howmany="1">
    <ps name="A64.control.branch_reg.ERET_64E_branch_reg" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if PSTATE.EL == EL0 then Undefined(); end;
AArch64_CheckForERetTrap(pac, use_key_a);
let target : bits(64) = ELR_ELx();

AArch64_ExceptionReturn(target, SPSR_ELx());</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
