EXT
Extract vector from pair of vectors
This instruction extracts the lowest vector elements from the
second source SIMD&FP register and the highest vector elements from the first
source SIMD&FP register,
concatenates the results into a vector,
and writes the vector to the destination SIMD&FP register vector.
The index value specifies the lowest vector element to extract from the
first source register, and consecutive elements are extracted from
the first, then second, source registers until the destination vector is filled.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
0
1
0
1
1
1
0
0
0
0
0
0
EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if Q == '0' && imm4[3] == '1' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let datasize : integer{} = 64 << UInt(Q);
let position : integer{} = 8 * UInt(imm4);
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
<index>
Is the lowest numbered byte element to be extracted,
Q
imm4[3]
<index>
0
0
UInt(imm4[2:0])
0
1
RESERVED
1
x
UInt(imm4)
AArch64_CheckFPAdvSIMDEnabled();
let hi : bits(datasize) = V{}(m);
let lo : bits(datasize) = V{}(n);
let concat : bits(datasize*2) = hi :: lo;
V{datasize}(d) = concat[(position+datasize)-1:position];
2026-03-12 12:23:09
2025-09_rel_asl1