FACGT
Floating-point absolute compare greater than (vector)
This instruction compares the absolute value of
each vector element in the
first source SIMD&FP register with the absolute value of
the corresponding
vector element in the second source SIMD&FP register
and if the first value is greater than
the second value sets every bit of the corresponding vector element
in the destination SIMD&FP register to one,
otherwise sets every bit of the corresponding vector element
in the destination SIMD&FP register to zero.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 4 classes:
Scalar half-precision
,
Scalar single-precision and double-precision
,
Vector half-precision
and
Vector single-precision and double-precision
0
1
1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
FACGT <Hd>, <Hn>, <Hm>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 16;
let datasize : integer{} = esize;
let elements : integer = 1;
0
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
FACGT <V><d>, <V><n>, <V><m>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 32 << UInt(sz);
let datasize : integer{} = esize;
let elements : integer = 1;
0
1
0
1
1
1
0
1
1
0
0
0
1
0
1
1
FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 16;
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if sz::Q == '10' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 32 << UInt(sz);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Hm>
Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
<V>
Is a width specifier,
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
<m>
Is the number of the second SIMD&FP source register, encoded in the "Rm" field.
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the "Vector half-precision" variant: is an arrangement specifier,
<T>
For the "Vector single-precision and double-precision" variant: is an arrangement specifier,
sz
Q
<T>
0
0
2S
0
1
4S
1
0
RESERVED
1
1
2D
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand1 : bits(datasize) = V{}(n);
let operand2 : bits(datasize) = V{}(m);
var element1 : bits(esize);
var element2 : bits(esize);
var test_passed : boolean;
let merge : boolean = elements == 1 && IsMerging(FPCR());
var result : bits(128) = if merge then V{128}(m) else Zeros{128};
for e = 0 to elements-1 do
element1 = operand1[e*:esize];
element2 = operand2[e*:esize];
element1 = FPAbs{esize}(element1, FPCR());
element2 = FPAbs{esize}(element2, FPCR());
test_passed = FPCompareGT{esize}(element1, element2, FPCR());
result[e*:esize] = if test_passed then Ones{esize} else Zeros{esize};
end;
V{128}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1