FCVTN, FCVTN2 (double to single-precision, single to half-precision)
Floating-point convert to lower precision narrow (vector)
This instruction reads each vector element
in the SIMD&FP source register, converts each result to half
the precision of the source element, writes
the final result to a vector, and writes the vector
to the lower or upper half of the destination SIMD&FP register.
The destination vector elements are half as long as the source vector elements.
The rounding mode is determined by the FPCR.
FCVTN writes the vector to the lower half of the
destination register and clears the upper half.
FCVTN2 writes the vector to the upper half of the
destination register without affecting the other bits of the register.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
0
FCVTN{2} <Vd>.<Tb>, <Vn>.<Ta>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let esize : integer{} = 16 << UInt(sz);
let datasize : integer{} = 64;
let part : integer = UInt(Q);
let elements : integer = datasize DIV esize;
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Tb>
Is an arrangement specifier,
sz
Q
<Tb>
0
0
4H
0
1
8H
1
0
2S
1
1
4S
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Ta>
Is an arrangement specifier,
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(2*datasize) = V{}(n);
var result : bits(datasize);
for e = 0 to elements-1 do
result[e*:esize] = FPConvert{esize, 2*esize}(operand[e*:(2*esize)], FPCR());
end;
Vpart{datasize}(d, part) = result;
2026-03-12 12:23:09
2025-09_rel_asl1