FCVTZS (scalar SIMD&FP) Floating-point convert to signed integer, rounding toward zero (scalar SIMD&FP) This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round toward Zero rounding mode, and writes the result to the SIMD&FP destination register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 1 1 1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 FCVTZS <Sd>, <Hn> 1 1 1 FCVTZS <Dd>, <Hn> 1 0 0 FCVTZS <Dd>, <Sn> 0 0 1 FCVTZS <Sd>, <Dn> if !IsFeatureImplemented(FEAT_FPRCVT) then EndOfDecode(Decode_UNDEF); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let fltsize : integer{} = 8 << UInt(ftype XOR '10'); <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. AArch64_CheckFPEnabled(); var fltval : bits(fltsize); var intval : bits(intsize); let merge : boolean = IsMerging(FPCR()); var result : bits(128) = if merge then V{128}(d) else Zeros{128}; fltval = V{fltsize}(n); intval = FPToFixed{intsize, fltsize}(fltval, 0, FALSE, FPCR(), FPRounding_ZERO); result[0+:intsize] = intval; V{128}(d) = result; 2026-03-12 12:23:09 2025-09_rel_asl1