FMINNMV
Floating-point minimum number across vector
This instruction compares all the
vector elements in the source SIMD&FP register,
and writes the smallest of the values
as a scalar to the destination SIMD&FP register.
All the values in this instruction are floating-point values.
Regardless of the value of FPCR.AH,
the behavior is as follows:
Negative zero compares less than positive zero.
If one value is numeric and the other is a quiet NaN,
the result is the numeric value.
When FPCR.DN is 0, if either value is a signaling NaN
or if both values are NaNs, the result is a quiet NaN.
When FPCR.DN is 1, if either value is a signaling NaN
or if both values are NaNs, the result is Default NaN.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision
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FMINNMV <V><d>, <Vn>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 16;
let datasize : integer{} = 64 << UInt(Q);
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FMINNMV S<d>, <Vn>.4S
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if sz::Q != '01' then EndOfDecode(Decode_UNDEF); end; // .4S only
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 32;
let datasize : integer{} = 64 << UInt(Q);
<V>
Is the destination width specifier, H.
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<T>
Is an arrangement specifier,
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(datasize) = V{}(n);
V{esize}(d) = FPReduce{esize, datasize}(ReduceOp_FMINNUM, operand, FPCR());
2026-03-12 12:23:09
2025-09_rel_asl1