FMMLA (widening, 8-bit floating-point to half-precision)
8-bit floating-point matrix multiply-accumulate to half-precision
This instruction performs the fused sum-of-products within each four adjacent 8-bit
elements while multiplying the 2×4 matrix of 8-bit floating-point values
held in each 64-bit segment of the first source vector by the 4×2 matrix
of 8-bit floating-point values in the corresponding segment of the second
source vector. The half-precision sum-of-products are scaled by
2-UInt(FPMR.LSCALE[3:0]), before being destructively added
without intermediate rounding to the 2x2 half-precision matrix in the
destination vector. This is equivalent to accumulating 4-way dot product
per destination element.
The 8-bit floating-point encoding format for the elements of the first source
vector is selected by FPMR.F8S1. The 8-bit floating-point
encoding format for the elements of the second source vector is selected by
FPMR.F8S2.
0
1
1
0
1
1
1
0
0
0
0
1
1
1
0
1
1
FMMLA <Vd>.8H, <Vn>.16B, <Vm>.16B
if !IsFeatureImplemented(FEAT_F8F16MM) then EndOfDecode(Decode_UNDEF); end;
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let d : integer = UInt(Rd);
<Vd>
Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
CheckFPMREnabled();
AArch64_CheckFPAdvSIMDEnabled();
let operand1 : bits(128) = V{}(n);
let operand2 : bits(128) = V{}(m);
let operand3 : bits(128) = V{}(d);
var result : bits(128);
var op1, op2, acc : bits(64);
for s = 0 to 1 do
op1 = operand1[s*:64];
op2 = operand2[s*:64];
acc = operand3[s*:64];
result[s*:64] = FP8MatMulAddFP{64}(acc, op1, op2, 4, FPCR(), FPMR());
end;
V{128}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1