FMOV (vector, immediate)
Floating-point move immediate (vector)
This instruction copies an immediate
floating-point constant into every element of the SIMD&FP destination register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
FMOV <Vd>.<T>, #<imm>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let rd : integer = UInt(Rd);
let datasize : integer{} = 64 << UInt(Q);
let imm8 : bits(8) = a::b::c::d::e::f::g::h;
let imm16 : bits(16) = imm8[7]::NOT(imm8[6])::Replicate{2}(imm8[6])::imm8[5:0]::Zeros{6};
let imm : bits(datasize) = Replicate{}(imm16);
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
FMOV <Vd>.<T>, #<imm>
1
1
FMOV <Vd>.2D, #<imm>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if cmode::op == '11111' then
// FMOV Dn,#imm is in main FP instruction set
if Q == '0' then EndOfDecode(Decode_UNDEF); end;
end;
let rd : integer = UInt(Rd);
let datasize : integer{} = 64 << UInt(Q);
let imm64 : bits(64) = AdvSIMDExpandImm(op, cmode, a::b::c::d::e::f::g::h);
let imm : bits(datasize) = Replicate{}(imm64);
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the "Half-precision" variant: is an arrangement specifier,
<T>
For the "Single-precision" variant: is an arrangement specifier,
<imm>
Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h". For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in A64 floating-point instructions.
AArch64_CheckFPAdvSIMDEnabled();
V{datasize}(rd) = imm;
2026-03-12 12:23:09
2025-09_rel_asl1