FRINTN (vector)
Floating-point round to integral, to nearest with ties to even (vector)
This instruction rounds a vector of floating-point values
in the SIMD&FP source register
to integral floating-point values of the same size using the
Round to Nearest rounding mode, and writes the
result to the SIMD&FP destination register.
A zero input
gives a zero result with the same sign, an infinite input gives an infinite
result with the same sign, and a NaN is
propagated as for normal arithmetic.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
FRINTN <Vd>.<T>, <Vn>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 16;
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
let exact : boolean = FALSE;
let rounding : FPRounding = FPRounding_TIEEVEN;
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1
1
1
0
0
1
0
0
0
0
1
1
0
0
0
1
0
FRINTN <Vd>.<T>, <Vn>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if sz::Q == '10' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 32 << UInt(sz);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
let exact : boolean = FALSE;
let rounding : FPRounding = FPRounding_TIEEVEN;
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the "Half-precision" variant: is an arrangement specifier,
<T>
For the "Single-precision and double-precision" variant: is an arrangement specifier,
sz
Q
<T>
0
0
2S
0
1
4S
1
0
RESERVED
1
1
2D
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(datasize) = V{}(n);
var result : bits(datasize);
var element : bits(esize);
for e = 0 to elements-1 do
element = operand[e*:esize];
result[e*:esize] = FPRoundInt{esize}(element, FPCR(), rounding, exact);
end;
V{datasize}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1