LDAXRB Load-acquire exclusive register byte This instruction derives an address from a base register value, loads a byte from memory, zero-extends it and writes it to a register. The memory access is atomic. The PE marks the physical address being accessed as an exclusive access. This exclusive access mark is checked by Store Exclusive instructions. See Synchronization and semaphores. If the destination register is not one of WZR or XZR, LDAXRB loads from memory with Acquire semantics. For more information about memory ordering semantics, see Load-Acquire, Load-AcquirePC, and Store-Release. For information about addressing modes, see Load/Store addressing modes. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. 0 0 0 0 1 0 0 0 0 1 0 (1) (1) (1) (1) (1) 1 (1) (1) (1) (1) (1) LDAXRB <Wt>, [<Xn|SP>{, #0}] let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let acqrel : boolean = t != 31; let tagchecked : boolean = n != 31; <Wt> Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. var address : bits(64); var data : bits(8); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescExLDST(MemOp_LOAD, acqrel, tagchecked, privileged, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; AArch64_SetExclusiveMonitors(address, 1, accdesc); data = Mem{8}(address, accdesc); X{32}(t) = ZeroExtend{32}(data); 2026-03-12 12:23:09 2025-09_rel_asl1