LDBFMIN, LDBFMINA, LDBFMINAL, LDBFMINL
Atomic BFloat16 minimum
This instruction atomically loads a 16-bit value from memory,
computes the BFloat16 minimum with the value held in a register,
and stores the result back to memory.
The value initially loaded from memory is returned in the destination register.
LDBFMINA and
LDBFMINAL load
from memory with acquire semantics.
LDBFMINL and
LDBFMINAL store
to memory with release semantics.
LDBFMIN has neither acquire nor release semantics.
This instruction:
Disables alternative floating-point behaviors, as if FPCR.AH
is 0.
Generates only the default NaN, as if FPCR.DN
is 1.
Does not modify the cumulative FPSR
exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
Disables trapped floating-point exceptions, as if the
FPCR trap enable bits
(IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
For more information about memory ordering semantics, see Load-Acquire, Store-Release.
For information about addressing modes, see
Load/Store addressing modes.
0
0
1
1
1
1
0
0
1
0
1
0
1
0
0
0
0
LDBFMIN <Hs>, <Ht>, [<Xn|SP>]
1
0
LDBFMINA <Hs>, <Ht>, [<Xn|SP>]
1
1
LDBFMINAL <Hs>, <Ht>, [<Xn|SP>]
0
1
LDBFMINL <Hs>, <Ht>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_LSFE) then EndOfDecode(Decode_UNDEF); end;
let t : integer = UInt(Rt);
let n : integer = UInt(Rn);
let s : integer = UInt(Rs);
let datasize : integer{} = 16;
let acquire : boolean = A == '1';
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;
<Hs>
Is the 16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Ht>
Is the 16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
AArch64_CheckFPEnabled();
var address : bits(64);
var value : bits(datasize);
var data : bits(datasize);
let accdesc : AccessDescriptor = CreateAccDescFPAtomicOp(MemAtomicOp_BFMIN, acquire,
release, tagchecked);
value = V{datasize}(s);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
let comparevalue : bits(datasize) = ARBITRARY : bits(datasize); // Irrelevant when not executing CAS
data = MemAtomic{datasize}(address, comparevalue, value, accdesc);
V{datasize}(t) = data;
2026-03-12 12:23:09
2025-09_rel_asl1