LDIAPP
Load-Acquire RCpc ordered pair of registers
This instruction calculates an address from
a base register value and an optional offset, loads two 32-bit words or two 64-bit
doublewords from memory, and writes them to two registers.
For information on single-copy atomicity and alignment requirements,
see Requirements for single-copy atomicity and
Alignment of data accesses.
The instruction also has memory ordering
semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release,
except that:
The Memory effects associated with Xt1/Wt1 are Ordered-before the Memory effects associated with Xt2/Wt2.
If the destination registers are not both WZR or not both XZR, LDIAPP loads
from memory with Acquire semantics.
There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release,
created by having a Store-Release followed by a Load-AcquirePC instruction.
The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer
does not make the write of the Store-Release globally observed.
For information about addressing modes, see Load/Store addressing modes.
LDIAPP has the same CONSTRAINED UNPREDICTABLE behavior as LDP. For information about this CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDP and LDIAPP.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
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LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8
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LDIAPP <Wt1>, <Wt2>, [<Xn|SP>]
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LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16
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LDIAPP <Xt1>, <Xt2>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_LRCPC3) then EndOfDecode(Decode_UNDEF); end;
let ispair : boolean = TRUE;
let postindex : boolean = opc2[0] == '0';
var wback : boolean = opc2[0] == '0';
<Wt1>
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Wt2>
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xt1>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xt2>
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let scale : integer{} = 2 + UInt(size[0]);
let datasize : integer{} = 8 << scale;
let offset : integer = if opc2[0] == '0' then (2 << scale) else 0;
let acqrel : boolean = t != 31 && t2 != 31;
let tagchecked : boolean = wback || n != 31;
var rt_unknown : boolean = FALSE;
var wb_unknown : boolean = FALSE;
if wback && (t == n || t2 == n) && n != 31 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_WBSUPPRESS => wback = FALSE; // writeback is suppressed
when Constraint_UNKNOWN => wb_unknown = TRUE; // writeback is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
if t == t2 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_LDPOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN => rt_unknown = TRUE; // result is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
var address : bits(64);
var data1 : bits(datasize);
var data2 : bits(datasize);
let dbytes : integer{} = datasize DIV 8;
let accdesc : AccessDescriptor = CreateAccDescLDAcqPC(tagchecked, ispair, acqrel, t, t2);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
if !postindex then
address = AddressAdd(address, offset, accdesc);
end;
var full_data : bits(2*datasize);
full_data = Mem{2*datasize}(address, accdesc);
if BigEndian(accdesc.acctype) then
data2 = full_data[(datasize-1):0];
data1 = full_data[(2*datasize-1):datasize];
else
data1 = full_data[(datasize-1):0];
data2 = full_data[(2*datasize-1):datasize];
end;
if rt_unknown then
data1 = ARBITRARY : bits(datasize);
data2 = ARBITRARY : bits(datasize);
end;
X{datasize}(t) = data1;
X{datasize}(t2) = data2;
if wback then
if wb_unknown then
address = ARBITRARY : bits(64);
elsif postindex then
address = AddressAdd(address, offset, accdesc);
end;
if n == 31 then
SP{64}() = address;
else
X{64}(n) = address;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1