LDNP
Load pair of registers, with non-temporal hint
This instruction calculates an
address from a base register value and an immediate offset,
loads two 32-bit words or
two 64-bit doublewords from memory,
and writes them to
two registers.
For information about addressing modes, see
Load/Store addressing modes.
For information about non-temporal pair instructions, see
Load/Store non-temporal pair.
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDNP.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
x
0
1
0
1
0
0
0
0
1
0
LDNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}]
1
LDNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let nontemporal : boolean = TRUE;
let scale : integer{} = 2 + UInt(opc[1]);
let datasize : integer{} = 8 << scale;
let offset : bits(64) = LSL(SignExtend{64}(imm7), scale);
let tagchecked : boolean = n != 31;
var rt_unknown : boolean = FALSE;
if t == t2 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_LDPOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN => rt_unknown = TRUE; // Result is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
<Wt1>
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Wt2>
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<imm>
For the "32-bit" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.
<imm>
For the "64-bit" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.
<Xt1>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xt2>
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
var address : bits(64);
let dbytes : integer{} = datasize DIV 8;
let privileged : boolean = PSTATE.EL != EL0;
let ispair : boolean = TRUE;
let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged,
tagchecked, ispair, t, t2);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
address = AddressAdd(address, offset, accdesc);
let data : bits(2*datasize) = Mem{2*datasize}(address, accdesc);
if rt_unknown then
X{datasize}(t) = ARBITRARY : bits(datasize);
elsif BigEndian(accdesc.acctype) then
X{datasize}(t2) = data[(datasize-1):0];
X{datasize}(t) = data[(2*datasize-1):datasize];
else
X{datasize}(t) = data[(datasize-1):0];
X{datasize}(t2) = data[(2*datasize-1):datasize];
end;
2026-03-12 12:23:09
2025-09_rel_asl1