LDRSH (immediate)
Load register signed halfword (immediate)
This instruction loads a halfword from
memory, sign-extends it to 32 bits or 64 bits, and writes the result
to a register.
The address that is used for the load is calculated from a
base register and an immediate offset.
For information about addressing modes, see
Load/Store addressing modes.
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRSH (immediate).
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
It has encodings from 3 classes:
Post-index
,
Pre-index
and
Unsigned offset
0
1
1
1
1
0
0
0
1
x
0
0
1
1
LDRSH <Wt>, [<Xn|SP>], #<simm>
0
LDRSH <Xt>, [<Xn|SP>], #<simm>
var wback : boolean = TRUE;
let postindex : boolean = TRUE;
let offset : bits(64) = SignExtend{}(imm9);
0
1
1
1
1
0
0
0
1
x
0
1
1
1
LDRSH <Wt>, [<Xn|SP>, #<simm>]!
0
LDRSH <Xt>, [<Xn|SP>, #<simm>]!
var wback : boolean = TRUE;
let postindex : boolean = FALSE;
let offset : bits(64) = SignExtend{}(imm9);
0
1
1
1
1
0
0
1
1
x
1
LDRSH <Wt>, [<Xn|SP>{, #<pimm>}]
0
LDRSH <Xt>, [<Xn|SP>{, #<pimm>}]
var wback : boolean = FALSE;
let postindex : boolean = FALSE;
let offset : bits(64) = LSL(ZeroExtend{64}(imm12), 1);
<Wt>
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<simm>
Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.
<Xt>
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
<pimm>
Is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let regsize : integer{} = 64 >> UInt(opc[0]);
let nontemporal : boolean = FALSE;
let tagchecked : boolean = wback || n != 31;
var c : Constraint;
var wb_unknown : boolean = FALSE;
if wback && n == t && n != 31 then
c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD);
assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_WBSUPPRESS => wback = FALSE; // Writeback is suppressed
when Constraint_UNKNOWN => wb_unknown = TRUE; // Writeback is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
var address : bits(64);
let privileged : boolean = PSTATE.EL != EL0;
let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged,
tagchecked, t);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
if !postindex then
address = AddressAdd(address, offset, accdesc);
end;
let data : bits(16) = Mem{16}(address, accdesc);
X{regsize}(t) = SignExtend{regsize}(data);
if wback then
if wb_unknown then
address = ARBITRARY : bits(64);
elsif postindex then
address = AddressAdd(address, offset, accdesc);
end;
if n == 31 then
SP{64}() = address;
else
X{64}(n) = address;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1