MVNI
Move inverted immediate (vector)
This instruction places the inverse of an immediate constant into every
vector element of the destination
SIMD&FP register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
0
1
0
1
1
1
1
0
0
0
0
0
0
1
1
0
x
0
MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}
0
x
x
0
MVNI <Vd>.<T>, #<imm8>{, LSL #<amount>}
1
1
0
x
MVNI <Vd>.<T>, #<imm8>, MSL #<amount>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
let rd : integer = UInt(Rd);
let datasize : integer{} = 64 << UInt(Q);
let imm64 : bits(64) = AdvSIMDExpandImm(op, cmode, a::b::c::d::e::f::g::h);
let imm : bits(datasize) = Replicate{}(imm64);
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the "16-bit shifted immediate" variant: is an arrangement specifier,
<T>
For the "32-bit shifted immediate" and "32-bit shifting ones" variants: is an arrangement specifier,
<imm8>
Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".
<amount>
For the "16-bit shifted immediate" variant: is the shift amount
cmode[1]
<amount>
0
0
1
8
defaulting to 0 if LSL is omitted.
<amount>
For the "32-bit shifted immediate" variant: is the shift amount
cmode[2:1]
<amount>
00
0
01
8
10
16
11
24
defaulting to 0 if LSL is omitted.
<amount>
For the "32-bit shifting ones" variant: is the shift amount
cmode[0]
<amount>
0
8
1
16
AArch64_CheckFPAdvSIMDEnabled();
V{datasize}(rd) = NOT(imm);
2026-03-12 12:23:09
2025-09_rel_asl1