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<instructionsection id="RCWSET" title="RCWSET, RCWSETA, RCWSETAL, RCWSETL -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
  </docvars>
  <heading>RCWSET, RCWSETA, RCWSETAL, RCWSETL</heading>
  <desc>
    <brief>
      <para>Read check write atomic bit set on doubleword in memory</para>
    </brief>
    <authored>
      <para>This instruction atomically loads
a 64-bit doubleword from memory, performs a bitwise OR with the complement of the value
held in a register on it, and conditionally stores the result back to memory.
Storing of the result back to memory is conditional on RCW Checks.
The value initially loaded from memory is returned in the destination register.
This instruction updates the condition flags based on the result of the update of memory.</para>
      <list type="unordered">
        <listitem>
          <content>If the destination register is not <value>XZR</value>, <instruction>RCWSETA</instruction> and <instruction>RCWSETAL</instruction> load from memory with acquire semantics.</content>
        </listitem>
        <listitem>
          <content>
            <instruction>RCWSETL</instruction> and <instruction>RCWSETAL</instruction> store to memory with release semantics.</content>
        </listitem>
        <listitem>
          <content>
            <instruction>RCWSET</instruction> has neither acquire nor release semantics.</content>
        </listitem>
      </list>
      <note>
        <para>This instruction is for performing atomic updates of translation table entries and not for general use.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
      </docvars>
      <iclassintro count="4"/>
      <arch_variants>
        <arch_variant feature="FEAT_THE" name="v8Ap9"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.memop.RCWSET_64_memop" tworows="1">
        <box hibit="31" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="VR" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="A" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="22" width="1" name="R" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" name="o3" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="RCWSET_64_memop" oneofinclass="4" oneof="4" label="RCWSET" bitdiffs="A == 0 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSET"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>RCWSET  </text><a hover="Is the 64-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="XsOrXZR">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="XtOrXZR__8">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="RCWSETA_64_memop" oneofinclass="4" oneof="4" label="RCWSETA" bitdiffs="A == 1 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSETA"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>RCWSETA  </text><a hover="Is the 64-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="XsOrXZR">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="XtOrXZR__8">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="RCWSETAL_64_memop" oneofinclass="4" oneof="4" label="RCWSETAL" bitdiffs="A == 1 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSETAL"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>RCWSETAL  </text><a hover="Is the 64-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="XsOrXZR">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="XtOrXZR__8">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="RCWSETL_64_memop" oneofinclass="4" oneof="4" label="RCWSETL" bitdiffs="A == 0 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSETL"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>RCWSETL  </text><a hover="Is the 64-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="XsOrXZR">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="XtOrXZR__8">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.memop.RCWSET_64_memop" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_THE) then EndOfDecode(Decode_UNDEF); end;
let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let soft : boolean = FALSE;

let acquire : boolean = A == '1' &amp;&amp; t != 31;
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RCWSET_64_memop, RCWSETA_64_memop, RCWSETAL_64_memop, RCWSETL_64_memop" symboldefcount="1">
      <symbol link="XsOrXZR">&lt;Xs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RCWSET_64_memop, RCWSETA_64_memop, RCWSETAL_64_memop, RCWSETL_64_memop" symboldefcount="1">
      <symbol link="XtOrXZR__8">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RCWSET_64_memop, RCWSETA_64_memop, RCWSETAL_64_memop, RCWSETL_64_memop" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.memop.RCWSET_64_memop" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if IsD128Enabled(PSTATE.EL) then Undefined(); end;

var address : bits(64);
let newdata : bits(64) = X{}(s);
var readdata : bits(64);
var nzcv : bits(4);

let accdesc : AccessDescriptor = CreateAccDescRCW(MemAtomicOp_ORR, soft, acquire, release,
                                                  tagchecked, t, s);

if n == 31 then
    CheckSPAlignment();
    address = SP{64}();
else
    address = X{64}(n);
end;

let compdata : bits(64) = ARBITRARY : bits(64);    // Irrelevant when not executing CAS
(nzcv, readdata) = MemAtomicRCW{64}(address, compdata, newdata, accdesc);

PSTATE.[N,Z,C,V] = nzcv;
X{64}(t) = readdata;    // Return the old value when t!=31</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
