RCWSWPP, RCWSWPPA, RCWSWPPAL, RCWSWPPL
Read check write swap quadword in memory
This instruction atomically loads
a 128-bit quadword from a memory location, and conditionally stores the value held in a
pair of registers back to the same memory location. Storing back to memory is conditional
on RCW Checks. The value initially loaded from memory is returned in
the same pair of registers. This instruction updates the condition flags based on the
result of the update of memory.
RCWSWPPA and RCWSWPPAL load from memory with acquire semantics.
RCWSWPPL and RCWSWPPAL store to memory with release semantics.
RCWSWPP has neither acquire nor release semantics.
This instruction is for performing atomic updates of translation table entries and not for general use.
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly CONSTRAINED UNPREDICTABLE behavior for A64 instructions.
0
0
0
1
1
0
0
1
1
1
0
1
0
0
0
0
0
RCWSWPP <Xt1>, <Xt2>, [<Xn|SP>]
1
0
RCWSWPPA <Xt1>, <Xt2>, [<Xn|SP>]
1
1
RCWSWPPAL <Xt1>, <Xt2>, [<Xn|SP>]
0
1
RCWSWPPL <Xt1>, <Xt2>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_D128) || !IsFeatureImplemented(FEAT_THE) then
EndOfDecode(Decode_UNDEF);
end;
if Rt == '11111' then EndOfDecode(Decode_UNDEF); end;
if Rt2 == '11111' then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let soft : boolean = FALSE;
let acquire : boolean = A == '1';
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;
var rt_unknown : boolean = FALSE;
if t == t2 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_LSE128OVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN => rt_unknown = TRUE; // result is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
<Xt1>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xt2>
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
if !IsD128Enabled(PSTATE.EL) then Undefined(); end;
var address : bits(64);
var value1 : bits(64);
var value2 : bits(64);
var newdata : bits(128);
var readdata : bits(128);
var nzcv : bits(4);
let accdesc : AccessDescriptor = CreateAccDescRCW(MemAtomicOp_SWP, soft, acquire, release,
tagchecked, t, t2, t, t2);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
value1 = X{64}(t);
value2 = X{64}(t2);
newdata = if BigEndian(accdesc.acctype) then value1::value2 else value2::value1;
let compdata : bits(128) = ARBITRARY : bits(128); // Irrelevant when not executing CAS
(nzcv, readdata) = MemAtomicRCW{128}(address, compdata, newdata, accdesc);
PSTATE.[N,Z,C,V] = nzcv;
if rt_unknown then
readdata = ARBITRARY : bits(128);
end;
if BigEndian(accdesc.acctype) then
X{64}(t) = readdata[127:64];
X{64}(t2) = readdata[63:0];
else
X{64}(t) = readdata[63:0];
X{64}(t2) = readdata[127:64];
end;
2026-03-12 12:23:09
2025-09_rel_asl1