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<instructionsection id="RORV" title="RORV -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="RORV"/>
  </docvars>
  <heading>RORV</heading>
  <desc>
    <brief>
      <para>Rotate right variable</para>
    </brief>
    <authored>
      <para>This instruction provides the value of the contents of a
register rotated by a variable number of bits. The bits that are
rotated off the right end are inserted into the vacated bit
positions on the left. The value of the second source register
modulo the register size in bits gives the number of
bits by which the first source register is right-shifted.</para>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="1">
    <alias_list_intro>This instruction is used by the alias </alias_list_intro>
    <aliasref aliaspageid="ROR_RORV" aliasfile="ror_rorv.xml" hover="Rotate right (register)" punct=".">
      <text>ROR (register)</text>
      <aliaspref>Unconditionally</aliaspref>
    </aliasref>
    <alias_list_outro> The alias is always the preferred disassembly.</alias_list_outro>
  </alias_list>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="RORV"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A64.dpreg.dp_2src.RORV_32_dp_2src" tworows="1">
        <box hibit="31" width="1" name="sf" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="30" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="op2" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="RORV_32_dp_2src" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RORV"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <asmtemplate><text>RORV  </text><a hover="Is the 32-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="WdOrWZR">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__3">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the &quot;Rm&quot; field." link="WmOrWZR__4">&lt;Wm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="RORV_64_dp_2src" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
        <docvars>
          <docvar key="datatype" value="64"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RORV"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <asmtemplate><text>RORV  </text><a hover="Is the 64-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="XdOrXZR__6">&lt;Xd&gt;</a><text>, </text><a hover="Is the 64-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="XnOrXZR__12">&lt;Xn&gt;</a><text>, </text><a hover="Is the 64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the &quot;Rm&quot; field." link="XmOrXZR__7">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.dpreg.dp_2src.RORV_32_dp_2src" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let datasize : integer{} = 32 &lt;&lt; UInt(sf);
let shift_type : <a link="ShiftType" file="shared_pseudocode.xml" hover="type ShiftType">ShiftType</a> = DecodeShift(op2);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RORV_32_dp_2src" symboldefcount="1">
      <symbol link="WdOrWZR">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_32_dp_2src" symboldefcount="1">
      <symbol link="WnOrWZR__3">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_32_dp_2src" symboldefcount="1">
      <symbol link="WmOrWZR__4">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_64_dp_2src" symboldefcount="1">
      <symbol link="XdOrXZR__6">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_64_dp_2src" symboldefcount="1">
      <symbol link="XnOrXZR__12">&lt;Xn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RORV_64_dp_2src" symboldefcount="1">
      <symbol link="XmOrXZR__7">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
  <ps_section howmany="1">
    <ps name="A64.dpreg.dp_2src.RORV_32_dp_2src" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">let operand2 : bits(datasize) = X{}(m);

X{datasize}(d) = ShiftReg{datasize}(n, shift_type, UInt(operand2) MOD datasize);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
