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<instructionsection id="RPRFM_reg" title="RPRFM -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="RPRFM"/>
    <docvar key="offset-type" value="off-reg"/>
  </docvars>
  <heading>RPRFM</heading>
  <desc>
    <brief>
      <para>Range prefetch memory</para>
    </brief>
    <authored>
      <para>This instruction signals the memory system that
data memory accesses from a specified range of addresses are likely to occur
in the near future. The instruction may also signal the memory system about
the likelihood of data reuse of the specified range of addresses.
The memory system can respond by taking actions that are
expected to speed up the memory accesses when they do occur,
such as prefetching locations within the specified address ranges
into one or more caches. The memory system may also exploit the data reuse
hints to decide whether to retain the data in other caches upon eviction
from the innermost caches or to discard it.</para>
      <para>The effect of an <instruction>RPRFM</instruction> instruction is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.
For more information, see <xref linkend="ARMARM_CEGGGIDE">Prefetch memory</xref>.</para>
      <para>An <instruction>RPRFM</instruction> instruction specifies the type of accesses and range of addresses using
the following parameters:</para>
      <list type="unordered">
        <listitem>
          <content>'Access type', encoded in <syntax>Rt&lt;0&gt;</syntax>, specifies:<list type="unordered">
              <listitem>
                <content>PLD for prefetch for load.</content>
              </listitem>
              <listitem>
                <content>PST for prefetch for store.</content>
              </listitem>
            </list>
          </content>
        </listitem>
        <listitem>
          <content>'Policy', encoded in <syntax>Rt&lt;2:1&gt;</syntax>, specifies:<list type="unordered">
              <listitem>
                <content>KEEP for retained or temporal prefetch, allocated in the cache normally.</content>
              </listitem>
              <listitem>
                <content>STRM for streaming or non-temporal prefetch, for data that is used only once.
If a streaming prefetch is specified, then the 'ReuseDistance' parameter is ignored.</content>
              </listitem>
            </list>
          </content>
        </listitem>
        <listitem>
          <content>'BaseAddress', in the 64-bit base register, holds the initial block address
for the accesses.</content>
        </listitem>
        <listitem>
          <content>'ReuseDistance', in the metadata register bits[63:60], indicates the maximum
number of bytes to be accessed by this PE before executing the next <instruction>RPRFM</instruction> instruction
that specifies the same range. This includes the total number of bytes inside and
outside of the range that will be accessed by the same PE. This parameter
can be used to influence cache eviction and replacement policies,
in order to retain the data in the most optimal levels of the memory hierarchy
after each access. If software cannot easily determine the amount of other
memory that will be accessed, these bits can be set to zero to indicate
that 'ReuseDistance' is not known. Otherwise, these four bits encode decreasing
powers of two in the range 512MiB (<binarynumber>0b0001</binarynumber>) to 32KiB (<binarynumber>0b1111</binarynumber>).</content>
        </listitem>
        <listitem>
          <content>'Stride', in the metadata register bits[59:38], is a signed, two's complement
integer encoding of the number of bytes to advance the block address after
'Length' bytes have been accessed, in the range -2MiB to +2MiB-1B.
A negative value indicates that the block address is advanced in a descending direction.</content>
        </listitem>
        <listitem>
          <content>'Count', in the metadata register bits[37:22], is an unsigned integer encoding
of the number of blocks of data to be accessed minus 1, representing the
range 1 to 65536 blocks. If 'Count' is 0, then the 'Stride' parameter
is ignored and only a single block of contiguous bytes from
'BaseAddress' to ('BaseAddress' + 'Length' - 1) is described.</content>
        </listitem>
        <listitem>
          <content>'Length', in the metadata register bits[21:0], is a signed, two's complement
integer encoding of the number of contiguous bytes to be accessed starting
from the current block address, without changing the block address,
in the range -2MiB to +2MiB-1B. A negative value indicates that
the bytes are accessed in a descending direction.</content>
        </listitem>
      </list>
      <note>
        <para>Software is expected to honor the parameters it provides to the <instruction>RPRFM</instruction> instruction,
and the same PE should access all locations in the range, in the direction specified by the sign
of the 'Length' and 'Stride' parameters. A range prefetch is considered active on a PE until all
locations in the range have been accessed by the PE. A range prefetch might also be inactivated
by the PE prior to completion, for example due to a software context switch or lack of hardware
resources.</para>
        <para>Software should not specify overlapping addresses in multiple active ranges. If a range is
expected to be accessed by both load and store instructions (read-modify-write), then a single
range with an 'Access type' parameter of <syntax>PST</syntax> (prefetch for store) should be specified.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="RPRFM"/>
        <docvar key="offset-type" value="off-reg"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_RPRFM" name="v8Ap9"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.ldst_regoff.RPRFM_R_ldst_regoff" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="29" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="27" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" name="VR" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="3" name="option" usename="1" settings="1" psbits="xxx">
          <c>x</c>
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="12" width="1" name="S" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1" settings="2" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>x</c>
          <c>x</c>
          <c>x</c>
        </box>
      </regdiagram>
      <encoding name="RPRFM_R_ldst_regoff" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="offset-type" value="off-reg"/>
          <docvar key="mnemonic" value="RPRFM"/>
        </docvars>
        <asmtemplate><text>RPRFM  (</text><a hover="Is the range prefetch operation, " link="RtSoption_rprfop">&lt;rprfop&gt;</a><text>|#</text><a hover="Is the range prefetch operation encoding as an immediate, in the range 0 to 63, encoded in &quot;option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:0&gt;&quot;. This syntax is only for encodings that are not representable using &lt;rprfop&gt;." link="RtSoption_imm6">&lt;imm6&gt;</a><text>), </text><a hover="Is the 64-bit name of the general-purpose register that holds an encoding of the metadata, encoded in the &quot;Rm&quot; field." link="XmOrXZR__3">&lt;Xm&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.ldst_regoff.RPRFM_R_ldst_regoff" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_RPRFM) then EndOfDecode(Decode_NOP); end;
let operation : bits(6) = option[2]::option[0]::S::Rt[2:0];
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RPRFM_R_ldst_regoff" symboldefcount="1">
      <symbol link="RtSoption_rprfop">&lt;rprfop&gt;</symbol>
      <definition encodedin="(option :: S :: Rt)">
        <intro>Is the range prefetch operation, </intro>
        <table class="valuetable">
          <tgroup cols="4">
            <thead>
              <row>
                <entry class="bitfield">option</entry>
                <entry class="bitfield">S</entry>
                <entry class="bitfield">Rt</entry>
                <entry class="symbol">&lt;rprfop&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">010</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11000</entry>
                <entry class="symbol">PLDKEEP</entry>
              </row>
              <row>
                <entry class="bitfield">010</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11001</entry>
                <entry class="symbol">PSTKEEP</entry>
              </row>
              <row>
                <entry class="bitfield">010</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11100</entry>
                <entry class="symbol">PLDSTRM</entry>
              </row>
              <row>
                <entry class="bitfield">010</entry>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">11101</entry>
                <entry class="symbol">PSTSTRM</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
        <after>For other encodings, use &lt;imm6&gt;.</after>
      </definition>
    </explanation>
    <explanation enclist="RPRFM_R_ldst_regoff" symboldefcount="1">
      <symbol link="RtSoption_imm6">&lt;imm6&gt;</symbol>
      <account encodedin="(option :: S :: Rt)">
        <intro>
          <para>Is the range prefetch operation encoding as an immediate, in the range 0 to 63, encoded in "option&lt;2&gt;:option&lt;0&gt;:S:Rt&lt;2:0&gt;". This syntax is only for encodings that are not representable using <syntax>&lt;rprfop&gt;</syntax>.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RPRFM_R_ldst_regoff" symboldefcount="1">
      <symbol link="XmOrXZR__3">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the general-purpose register that holds an encoding of the metadata, encoded in the "Rm" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RPRFM_R_ldst_regoff" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.ldst_regoff.RPRFM_R_ldst_regoff" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">let address : bits(64)  = if n == 31 then SP{64}() else X{64}(n);
let metadata : bits(64) = X{}(m);
let stride : integer = SInt(metadata[59:38]);
let count : integer  = UInt(metadata[37:22]) + 1;
let length : integer = SInt(metadata[21:0]);
var reuse : integer;

if metadata[63:60] == '0000' then
    reuse = -1; // Not known
else
    reuse = 32768 &lt;&lt; (15 - UInt(metadata[63:60]));
end;

Hint_RangePrefetch(address, length, stride, count, reuse, operation);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
