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<instructionsection id="setffr_f" title="SETFFR -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="SETFFR"/>
  </docvars>
  <heading>SETFFR</heading>
  <desc>
    <brief>
      <para>Initialize the first-fault register to all true</para>
    </brief>
    <authored>
      <para>This instruction initializes the first-fault register (<asm-code>FFR</asm-code>) to all true
prior to a sequence of first-fault or non-fault loads.  This instruction is unpredicated.</para>
      <para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
    </authored>
    <predicated>False</predicated>
    <sm_policy>SM_0_only</sm_policy>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="SETFFR"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_SVE" name="v8Ap2 &amp;&amp; PROFILE_A"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.sve.sve_pred_wrffr.sve_int_setffr.setffr_f_" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="21" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="18" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="17" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="8" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="5" settings="5">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
      </regdiagram>
      <encoding name="setffr_f_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="sve"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SETFFR"/>
        </docvars>
        <asmtemplate><text>SETFFR</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.sve.sve_pred_wrffr.sve_int_setffr.setffr_f_" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all"/>
  <ps_section howmany="1">
    <ps name="A64.sve.sve_pred_wrffr.sve_int_setffr.setffr_f_" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">CheckNonStreamingSVEEnabled();
let VL : integer{} = CurrentVL();
let PL : integer{} = VL DIV 8;
FFR{PL}() = Ones{PL};</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
