SHA512SU1 SHA512 schedule update 1 This instruction takes the values from the three source SIMD&FP registers and produces a 128-bit output value that combines the gamma1 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. 1 1 0 0 1 1 1 0 0 1 1 1 0 0 0 1 0 SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D if !IsFeatureImplemented(FEAT_SHA512) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); <Vd> Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. <Vn> Is the name of the second SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the third SIMD&FP source register, encoded in the "Rm" field. AArch64_CheckFPAdvSIMDEnabled(); var sig1 : bits(64); var Vtmp : bits(128); let x : bits(128) = V{}(n); let y : bits(128) = V{}(m); let w : bits(128) = V{}(d); sig1 = ROR(x[127:64], 19) XOR ROR(x[127:64], 61) XOR ('000000'::x[127:70]); Vtmp[127:64] = w[127:64] + sig1 + y[127:64]; sig1 = ROR(x[63:0], 19) XOR ROR(x[63:0], 61) XOR ('000000'::x[63:6]); Vtmp[63:0] = w[63:0] + sig1 + y[63:0]; V{128}(d) = Vtmp; 2026-03-12 12:23:09 2025-09_rel_asl1