SM3SS1 SM3SS1 This instruction rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. 1 1 0 0 1 1 1 0 0 1 0 0 SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S if !IsFeatureImplemented(FEAT_SM3) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let a : integer{} = UInt(Ra); <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. <Va> Is the name of the third SIMD&FP source register, encoded in the "Ra" field. AArch64_CheckFPAdvSIMDEnabled(); let Vm : bits(128) = V{}(m); let Vn : bits(128) = V{}(n); let Va : bits(128) = V{}(a); var result : bits(128); result[127:96] = ROL((ROL(Vn[127:96], 12) + Vm[127:96] + Va[127:96]), 7); result[95:0] = Zeros{96}; V{128}(d) = result; 2026-03-12 12:23:09 2025-09_rel_asl1