SM3TT1A
SM3TT1A
This instruction takes three 128-bit vectors from three source SIMD&FP
registers and a 2-bit immediate index value, and returns a 128-bit
result in the destination SIMD&FP register. It performs a
three-way exclusive-OR of the three 32-bit fields held in the upper
three elements of the first source vector, and adds the resulting
32-bit value and the following three other 32-bit values:
The bottom 32-bit element of the first source vector, Vd, that was used for
the three-way exclusive-OR.
The result of the exclusive-OR of the top 32-bit element of the
second source vector, Vn, with a rotation left by 12 of the top
32-bit element of the first source vector.
A 32-bit element indexed out of the third source vector, Vm.
The result of this addition is returned as the top element of the
result. The other elements of the result are taken from elements of
the first source vector, with the element returned in bits<63:32>
being rotated left by 9.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
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SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]
if !IsFeatureImplemented(FEAT_SM3) then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let i : integer = UInt(imm2);
<Vd>
Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.
<Vn>
Is the name of the second SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the third SIMD&FP source register, encoded in the "Rm" field.
<imm2>
Is a 32-bit element indexed out of <Vm>, encoded in "imm2".
AArch64_CheckFPAdvSIMDEnabled();
let Vm : bits(128) = V{}(m);
let Vn : bits(128) = V{}(n);
let Vd : bits(128) = V{}(d);
var WjPrime : bits(32);
var result : bits(128);
var TT1 : bits(32);
var SS2 : bits(32);
WjPrime = Vm[i*:32];
SS2 = Vn[127:96] XOR ROL(Vd[127:96], 12);
TT1 = Vd[63:32] XOR (Vd[127:96] XOR Vd[95:64]);
TT1 = (TT1 + Vd[31:0] + SS2 + WjPrime)[31:0];
result[31:0] = Vd[63:32];
result[63:32] = ROL(Vd[95:64], 9);
result[95:64] = Vd[127:96];
result[127:96] = TT1;
V{128}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1