SM3TT2B SM3TT2B This instruction takes three 128-bit vectors from three source SIMD&FP registers, and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a 32-bit majority function between the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values: The bottom 32-bit element of the first source vector, Vd, that was used for the 32-bit majority function. The 32-bit element held in the top 32 bits of the second source vector, Vn. A 32-bit element indexed out of the third source vector, Vm. A three-way exclusive-OR is performed of the result of this addition, the result of the addition rotated left by 9, and the result of the addition rotated left by 17. The result of this exclusive-OR is returned as the top element of the returned result. The other elements of this result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 19. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. 1 1 0 0 1 1 1 0 0 1 0 1 0 1 1 SM3TT2B <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>] if !IsFeatureImplemented(FEAT_SM3) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let i : integer = UInt(imm2); <Vd> Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field. <Vn> Is the name of the second SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the third SIMD&FP source register, encoded in the "Rm" field. <imm2> Is a 32-bit element indexed out of <Vm>, encoded in "imm2". AArch64_CheckFPAdvSIMDEnabled(); let Vm : bits(128) = V{}(m); let Vn : bits(128) = V{}(n); let Vd : bits(128) = V{}(d); var Wj : bits(32); var result : bits(128); var TT2 : bits(32); Wj = Vm[i*:32]; TT2 = (Vd[127:96] AND Vd[95:64]) OR (NOT(Vd[127:96]) AND Vd[63:32]); TT2 = (TT2 + Vd[31:0] + Vn[127:96] + Wj)[31:0]; result[31:0] = Vd[63:32]; result[63:32] = ROL(Vd[95:64], 19); result[95:64] = Vd[127:96]; result[127:96] = TT2 XOR ROL(TT2, 9) XOR ROL(TT2, 17); V{128}(d) = result; 2026-03-12 12:23:09 2025-09_rel_asl1