SQRSHL
Signed saturating rounding shift left (register)
This instruction takes each vector element in the first
source SIMD&FP register, shifts it by a value from the least
significant byte of the corresponding vector element of the second
source SIMD&FP register, places the results into a vector,
and writes the vector to the destination
SIMD&FP register.
If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.
The results are
rounded. For truncated results, see SQSHL.
If overflow occurs with any of the results, those results are saturated. If saturation occurs,
the cumulative saturation bit
FPSR.QC is set.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
0
1
1
1
1
0
1
0
1
0
1
1
1
SQRSHL <V><d>, <V><n>, <V><m>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if S == '0' && size != '11' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let unsigned : boolean = FALSE;
let rounding : boolean = TRUE;
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = esize;
let elements : integer = 1;
0
0
0
1
1
1
0
1
0
1
0
1
1
1
SQRSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size::Q == '110' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let unsigned : boolean = FALSE;
let rounding : boolean = TRUE;
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
<V>
Is a width specifier,
size
<V>
00
B
01
H
10
S
11
D
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the first SIMD&FP source register, encoded in the "Rn" field.
<m>
Is the number of the second SIMD&FP source register, encoded in the "Rm" field.
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
size
Q
<T>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
0
RESERVED
11
1
2D
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand1 : bits(datasize) = V{}(n);
let operand2 : bits(datasize) = V{}(m);
var result : bits(datasize);
var sat : boolean;
for e = 0 to elements-1 do
var element : integer = SInt(operand1[e*:esize]);
var shift : integer = ShiftSat(SInt(operand2[e*:esize][7:0]), esize);
if shift >= 0 then // left shift
element = element << shift;
else // right shift
shift = -shift;
element = RShr(element, shift, rounding);
end;
(result[e*:esize], sat) = SatQ{esize}(element, unsigned);
if sat then FPSR().QC = '1'; end;
end;
V{datasize}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1