SQRSHRN, SQRSHRN2
Signed saturating rounded shift right narrow (immediate)
This instruction reads
each vector element in the
source SIMD&FP
register,
right shifts each result by an immediate value,
saturates each shifted result to a value
that is half the original width,
puts the final result into a vector,
and writes the vector to the
lower or upper half of the destination SIMD&FP register.
All the values in this instruction are signed integer values.
The destination vector elements are half as long as the source vector elements.
The results are rounded. For truncated results, see
SQSHRN.
The SQRSHRN instruction writes the vector
to the lower half of the
destination register and clears the upper half.
The SQRSHRN2 instruction writes the vector
to the upper half of the
destination register without affecting the other bits of the register.
If saturation occurs, the cumulative saturation bit
FPSR.QC is set.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
0
1
1
1
1
1
0
!= 0000
1
0
0
1
1
1
SQRSHRN <Vb><d>, <Va><n>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if immh == '0000' then EndOfDecode(Decode_UNDEF); end;
if immh[3] == '1' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << HighestSetBitNZ(immh[2:0]);
let datasize : integer{} = esize;
let elements : integer = 1;
let part : integer = 0;
let shift : integer = (2 * esize) - UInt(immh::immb);
let round : boolean = TRUE;
let unsigned : boolean = FALSE;
0
0
0
1
1
1
1
0
!= 0000
1
0
0
1
1
1
SQRSHRN{2} <Vd>.<Tb>, <Vn>.<Ta>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if immh[3] == '1' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << HighestSetBitNZ(immh[2:0]);
let datasize : integer{} = 64;
let part : integer = UInt(Q);
let elements : integer = datasize DIV esize;
let shift : integer = (2 * esize) - UInt(immh::immb);
let round : boolean = TRUE;
let unsigned : boolean = FALSE;
<Vb>
Is the destination width specifier,
immh
<Vb>
0001
B
001x
H
01xx
S
1xxx
RESERVED
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<Va>
Is the source width specifier,
immh
<Va>
0001
H
001x
S
01xx
D
1xxx
RESERVED
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
<shift>
For the "Scalar" variant: is the right shift amount, in the range 1 to the destination operand width in bits,
immh
<shift>
0001
16 - UInt(immh :: immb)
001x
32 - UInt(immh :: immb)
01xx
64 - UInt(immh :: immb)
1xxx
RESERVED
<shift>
For the "Vector" variant: is the right shift amount, in the range 1 to the destination element width in bits,
immh
<shift>
0001
16 - UInt(immh :: immb)
001x
32 - UInt(immh :: immb)
01xx
64 - UInt(immh :: immb)
1xxx
RESERVED
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Tb>
Is an arrangement specifier,
immh
Q
<Tb>
0001
0
8B
0001
1
16B
001x
0
4H
001x
1
8H
01xx
0
2S
01xx
1
4S
1xxx
x
RESERVED
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Ta>
Is an arrangement specifier,
immh
<Ta>
0001
8H
001x
4S
01xx
2D
1xxx
RESERVED
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(datasize*2) = V{}(n);
var result : bits(datasize);
var sat : boolean;
for e = 0 to elements-1 do
let opelt : bits(2*esize) = operand[e*:(2*esize)];
if unsigned then
let element : integer = RShr(UInt(opelt), shift, round);
(result[e*:esize], sat) = UnsignedSatQ{esize}(element);
else
let element : integer = RShr(SInt(opelt), shift, round);
(result[e*:esize], sat) = SignedSatQ{esize}(element);
end;
if sat then FPSR().QC = '1'; end;
end;
Vpart{datasize}(d, part) = result;
2026-03-12 12:23:09
2025-09_rel_asl1