ST64BV
Single-copy atomic 64-byte store with status result
This instruction stores eight 64-bit doublewords from
consecutive registers to a memory location, and writes the status result of the store to
a register.
The store starts at register Xt, with the data being formed as Data[511:0] = X(t+7)::X(t+6)::X(t+5)::X(t+4)::X(t+3)::X(t+2)::X(t+1)::Xt.
The data is stored atomically and is required to be 64-byte aligned.
It is IMPLEMENTATION DEFINED which memory locations support this instruction.
A memory location that supports ST64BV also supports
ST64BV0.
For more information, including about the memory types accessible and how the accesses are
performed, see Single-copy atomic 64-byte load/store.
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ST64BV <Xs>, <Xt>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_LS64_V) then EndOfDecode(Decode_UNDEF); end;
if Rt[4:3] == '11' || Rt[0] == '1' then EndOfDecode(Decode_UNDEF); end;
let withstatus : boolean = TRUE;
let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let tagchecked : boolean = n != 31;
<Xs>
Is the 64-bit name of the general-purpose register into which the status result of this instruction is written, encoded in the "Rs" field.
The value returned is:
0xFFFFFFFF_FFFFFFFF
If the memory location accessed does not support this instruction. In this case, the value at the memory location is UNKNOWN.
!= 0xFFFFFFFF_FFFFFFFF
If the memory location accessed does support this instruction. In this case, the peripheral that provides the response defines the returned value and provides information on the state of the memory update at the memory location.
If XZR is used, then the return value is ignored.
<Xt>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
CheckST64BVEnabled();
var data : bits(512);
var address : bits(64);
var value : bits(64);
let accdesc : AccessDescriptor = CreateAccDescLS64(MemOp_STORE, withstatus, tagchecked);
for i = 0 to 7 do
value = X{64}(t+i);
if BigEndian(accdesc.acctype) then value = BigEndianReverse{64}(value); end;
data[63+64*i : 64*i] = value;
end;
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
let status : bits(64) = MemStore64BWithRet(address, data, accdesc);
if s != 31 then X{64}(s) = status; end;
2026-03-12 12:23:09
2025-09_rel_asl1