STGM
Store Allocation Tag multiple
This instruction writes a naturally aligned block of N Allocation Tags,
where the size of N is identified in GMID_EL1.BS,
and the Allocation Tag written to address A is taken from the
source register at 4*A<7:4>+3:4*A<7:4>.
This instruction is UNDEFINED at EL0.
This instruction generates an Unchecked access.
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STGM <Xt>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_MTE2) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
<Xt>
Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
if PSTATE.EL == EL0 then Undefined(); end;
let data : bits(64) = X{}(t);
var address : bits(64);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
let size : integer{} = 4 * (2 ^ (UInt(GMID_EL1().BS)));
address = AlignDownSize(address, size);
let count : integer = size >> LOG2_TAG_GRANULE;
var index : integer = UInt(address[LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE]);
let curraddress : bits(64) = address;
let stzgm : boolean = FALSE;
let accdesc : AccessDescriptor = CreateAccDescLDGSTG(MemOp_STORE, stzgm, t);
for i = 0 to count-1 do
let tag : bits(4) = data[index*:4];
AArch64_MemTag(address, accdesc) = tag;
address = AddressIncrement(address, TAG_GRANULE, accdesc);
index = index + 1;
end;
2026-03-12 12:23:09
2025-09_rel_asl1