STGP
Store Allocation Tag and pair of registers
This instruction stores an Allocation Tag and two
64-bit doublewords to memory, from two registers. The address used for the
store is calculated from the base register and an immediate signed offset
scaled by the Tag Granule. The Allocation Tag is calculated from the Logical
Address Tag in the base register.
This instruction generates an Unchecked access.
It has encodings from 3 classes:
Post-index
,
Pre-index
and
Signed offset
0
1
1
0
1
0
0
0
1
0
STGP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE);
let writeback : boolean = TRUE;
let postindex : boolean = TRUE;
0
1
1
0
1
0
0
1
1
0
STGP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE);
let writeback : boolean = TRUE;
let postindex : boolean = FALSE;
0
1
1
0
1
0
0
1
0
0
STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE);
let writeback : boolean = FALSE;
let postindex : boolean = FALSE;
<Xt1>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xt2>
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<imm>
For the "Post-index" and "Pre-index" variants: is the signed immediate offset, a multiple of 16 in the range -1024 to 1008, encoded in the "simm7" field.
<imm>
For the "Signed offset" variant: is the optional signed immediate offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "simm7" field.
var address : bits(64);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
let stzgm : boolean = FALSE;
let ispair : boolean = TRUE;
let accdesc : AccessDescriptor = CreateAccDescLDGSTG(MemOp_STORE, stzgm, ispair, t, t2);
if !postindex then
address = AddressAdd(address, offset, accdesc);
end;
if !IsAlignedSize(address, TAG_GRANULE) then
let fault : FaultRecord = AlignmentFault(accdesc, address);
AArch64_Abort(fault);
end;
let data : bits(128) = (if BigEndian(accdesc.acctype) then X{64}(t) ::X{64}(t2)
else X{64}(t2)::X{64}(t));
Mem{128}(address, accdesc) = data;
AArch64_MemTag(address, accdesc) = AArch64_AllocationTagFromAddress(address);
if writeback then
if postindex then
address = AddressAdd(address, offset, accdesc);
end;
if n == 31 then
SP{64}() = address;
else
X{64}(n) = address;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1