STLUR (SIMD&FP) Store-release SIMD&FP register (unscaled offset) This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an optional immediate offset. The instruction has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. 0 1 1 1 0 1 x 0 0 1 0 0 0 0 STLUR <Bt>, [<Xn|SP>{, #<simm>}] 0 1 0 STLUR <Ht>, [<Xn|SP>{, #<simm>}] 1 0 0 STLUR <St>, [<Xn|SP>{, #<simm>}] 1 1 0 STLUR <Dt>, [<Xn|SP>{, #<simm>}] 0 0 1 STLUR <Qt>, [<Xn|SP>{, #<simm>}] if !IsFeatureImplemented(FEAT_FP) || !IsFeatureImplemented(FEAT_LRCPC3) then EndOfDecode(Decode_UNDEF); end; if opc[1] == '1' && size != '00' then EndOfDecode(Decode_UNDEF); end; let scale : integer{} = if opc[1] == '1' then 4 else UInt(size); let offset : bits(64) = SignExtend{}(imm9); <Bt> Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <simm> Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field. <Ht> Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <St> Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <Dt> Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. <Qt> Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let datasize : integer{} = 8 << scale; let nontemporal : boolean = FALSE; let tagchecked : boolean = n != 31; AArch64_CheckFPAdvSIMDEnabled(); var address : bits(64); let accdesc : AccessDescriptor = CreateAccDescASIMDAcqRel(MemOp_STORE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; address = AddressAdd(address, offset, accdesc); Mem{datasize}(address, accdesc) = V{datasize}(t); 2026-03-12 12:23:09 2025-09_rel_asl1