STTNP (SIMD&FP)
Store unprivileged pair of SIMD&FP registers, with non-temporal hint
This instruction stores a pair of SIMD&FP registers to memory, issuing a hint to the
memory system that the access is non-temporal. The address used for the store is
calculated from an address from a base register value and an immediate offset.
For information about non-temporal pair instructions, see
Load/Store SIMD and Floating-point non-temporal pair.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
Explicit Memory effects produced by the instruction behave as if the instruction was
executed at EL0 if the Effective value of
PSTATE.UAO is 0 and either:
The instruction is executed at EL1.
The instruction is executed at EL2 when the Effective value
of HCR_EL2().{E2H, TGE} is '11'.
Otherwise, the Explicit Memory effects operate with the restrictions determined by
the Exception level at which the instruction is executed.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
1
1
1
0
1
1
0
0
0
0
STTNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]
if !IsFeatureImplemented(FEAT_FP) || !IsFeatureImplemented(FEAT_LSUI) then
EndOfDecode(Decode_UNDEF);
end;
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let nontemporal : boolean = TRUE;
let datasize : integer{} = 128;
let offset : bits(64) = LSL(SignExtend{64}(imm7), 4);
let tagchecked : boolean = n != 31;
<Qt1>
Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.
<Qt2>
Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<imm>
Is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.
AArch64_CheckFPEnabled();
var address : bits(64);
let dbytes : integer{} = datasize DIV 8;
let privileged : boolean = AArch64_IsUnprivAccessPriv();
let ispair : boolean = TRUE;
let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked,
privileged, ispair);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
address = AddressAdd(address, offset, accdesc);
var data : bits(2*datasize);
if BigEndian(accdesc.acctype) then
data = V{datasize}(t) :: V{datasize}(t2);
else
data = V{datasize}(t2) :: V{datasize}(t);
end;
Mem{2*datasize}(address, accdesc) = data;
2026-03-12 12:23:09
2025-09_rel_asl1