STZ2G
Store Allocation Tags, zeroing
This instruction stores an Allocation Tag to two Tag Granules of
memory, zeroing the associated data locations. The address used for the store
is calculated from the base register and an immediate signed offset scaled
by the Tag Granule. The Allocation Tag is calculated from the Logical Address
Tag in the source register.
This instruction generates an Unchecked access.
It has encodings from 3 classes:
Post-index
,
Pre-index
and
Signed offset
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STZ2G <Xt|SP>, [<Xn|SP>], #<simm>
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let offset : bits(64) = LSL(SignExtend{64}(imm9), LOG2_TAG_GRANULE);
let writeback : boolean = TRUE;
let postindex : boolean = TRUE;
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STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]!
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let offset : bits(64) = LSL(SignExtend{64}(imm9), LOG2_TAG_GRANULE);
let writeback : boolean = TRUE;
let postindex : boolean = FALSE;
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STZ2G <Xt|SP>, [<Xn|SP>{, #<simm>}]
if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let offset : bits(64) = LSL(SignExtend{64}(imm9), LOG2_TAG_GRANULE);
let writeback : boolean = FALSE;
let postindex : boolean = FALSE;
<Xt|SP>
Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<simm>
Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.
var address : bits(64);
var address2 : bits(64);
let data : bits(64) = if t == 31 then SP{64}() else X{64}(t);
let tag : bits(4) = AArch64_AllocationTagFromAddress(data);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
let stzgm : boolean = FALSE;
let ispair : boolean = TRUE;
let accdesc : AccessDescriptor = CreateAccDescLDGSTG(MemOp_STORE, stzgm, ispair, t, t);
if !postindex then
address = AddressAdd(address, offset, accdesc);
end;
address2 = AddressIncrement(address, TAG_GRANULE, accdesc);
if !IsAlignedSize(address, TAG_GRANULE) then
let fault : FaultRecord = AlignmentFault(accdesc, address);
AArch64_Abort(fault);
end;
Mem{16*TAG_GRANULE}(address, accdesc) = Zeros{TAG_GRANULE * 16};
AArch64_MemTag(address , accdesc) = tag;
AArch64_MemTag(address2, accdesc) = tag;
if writeback then
if postindex then
address = AddressAdd(address, offset, accdesc);
end;
if n == 31 then
SP{64}() = address;
else
X{64}(n) = address;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1