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<instructionsection id="SWPB" title="SWPB, SWPAB, SWPALB, SWPLB -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
  </docvars>
  <heading>SWPB, SWPAB, SWPALB, SWPLB</heading>
  <desc>
    <brief>
      <para>Swap byte in memory</para>
    </brief>
    <authored>
      <para>This instruction
atomically loads an 8-bit byte from a memory location,
and stores the value held in a register back to the same memory location.
The value initially loaded from memory is returned in the destination register.</para>
      <list type="unordered">
        <listitem>
          <content>If the destination register is not <value>WZR</value>, <instruction>SWPAB</instruction> and <instruction>SWPALB</instruction> load from memory with acquire semantics.</content>
        </listitem>
        <listitem>
          <content>
            <instruction>SWPLB</instruction> and <instruction>SWPALB</instruction> store to memory with release semantics.</content>
        </listitem>
        <listitem>
          <content>
            <instruction>SWPB</instruction> has neither acquire nor release semantics.</content>
        </listitem>
      </list>
      <para>For more information about memory ordering semantics, see <xref linkend="ARMARM_BEIHCHEF">Load-Acquire, Store-Release</xref>.</para>
      <para>For information about addressing modes, see
<xref linkend="ARMARM_CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
      </docvars>
      <iclassintro count="4"/>
      <arch_variants>
        <arch_variant feature="FEAT_LSE" name="v8Ap1"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.memop.SWPB_32_memop" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="2" psbits="xx">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="29" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="26" name="VR" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="25" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="23" width="1" name="A" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="22" width="1" name="R" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" name="o3" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="SWPB_32_memop" oneofinclass="4" oneof="4" label="SWPB" bitdiffs="A == 0 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SWPB"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SWPB  </text><a hover="Is the 32-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="WsOrWZR__2">&lt;Ws&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="WtOrWZR__2">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="SWPAB_32_memop" oneofinclass="4" oneof="4" label="SWPAB" bitdiffs="A == 1 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SWPAB"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>SWPAB  </text><a hover="Is the 32-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="WsOrWZR__2">&lt;Ws&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="WtOrWZR__2">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="SWPALB_32_memop" oneofinclass="4" oneof="4" label="SWPALB" bitdiffs="A == 1 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SWPALB"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SWPALB  </text><a hover="Is the 32-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="WsOrWZR__2">&lt;Ws&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="WtOrWZR__2">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="SWPLB_32_memop" oneofinclass="4" oneof="4" label="SWPLB" bitdiffs="A == 0 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SWPLB"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>SWPLB  </text><a hover="Is the 32-bit name of the general-purpose register to be stored, encoded in the &quot;Rs&quot; field." link="WsOrWZR__2">&lt;Ws&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="WtOrWZR__2">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.memop.SWPB_32_memop" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF); end;

let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);

let acquire : boolean = A == '1' &amp;&amp; Rt != '11111';
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SWPB_32_memop, SWPAB_32_memop, SWPALB_32_memop, SWPLB_32_memop" symboldefcount="1">
      <symbol link="WsOrWZR__2">&lt;Ws&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SWPB_32_memop, SWPAB_32_memop, SWPALB_32_memop, SWPLB_32_memop" symboldefcount="1">
      <symbol link="WtOrWZR__2">&lt;Wt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SWPB_32_memop, SWPAB_32_memop, SWPALB_32_memop, SWPLB_32_memop" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.memop.SWPB_32_memop" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">var address : bits(64);
var data : bits(8);
var store_value : bits(8);

let privileged : boolean = PSTATE.EL != EL0;
let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release,
                                                       tagchecked, privileged, t, s);

if n == 31 then
    CheckSPAlignment();
    address = SP{64}();
else
    address = X{64}(n);
end;

store_value = X{8}(s);

let comparevalue : bits(8) = ARBITRARY : bits(8); // Irrelevant when not executing CAS
data = MemAtomic{8}(address, comparevalue, store_value, accdesc);

X{32}(t) = ZeroExtend{32}(data);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
