SWPP, SWPPA, SWPPAL, SWPPL
Swap quadword in memory
This instruction atomically loads a 128-bit quadword from a memory location, and stores the value
held in a pair of registers back to the same memory location. The value initially loaded from
memory is returned in the same pair of registers.
SWPPA and SWPPAL load from memory with acquire semantics.
SWPPL and SWPPAL store to memory with release semantics.
SWPP has neither acquire nor release semantics.
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly CONSTRAINED UNPREDICTABLE behavior for A64 instructions.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
SWPP <Xt1>, <Xt2>, [<Xn|SP>]
1
0
SWPPA <Xt1>, <Xt2>, [<Xn|SP>]
1
1
SWPPAL <Xt1>, <Xt2>, [<Xn|SP>]
0
1
SWPPL <Xt1>, <Xt2>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_LSE128) then EndOfDecode(Decode_UNDEF); end;
if Rt == '11111' then EndOfDecode(Decode_UNDEF); end;
if Rt2 == '11111' then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let acquire : boolean = A == '1';
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;
var rt_unknown : boolean = FALSE;
if t == t2 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_LSE128OVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN => rt_unknown = TRUE; // result is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
<Xt1>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xt2>
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
var address : bits(64);
let value1 : bits(64) = X{}(t);
let value2 : bits(64) = X{}(t2);
var data : bits(128);
var store_value : bits(128);
let privileged : boolean = PSTATE.EL != EL0;
let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release,
tagchecked, privileged, t, t2, t, t2);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
store_value = if BigEndian(accdesc.acctype) then value1::value2 else value2::value1;
let comparevalue : bits(128) = ARBITRARY : bits(128); // Irrelevant when not executing CAS
data = MemAtomic{128}(address, comparevalue, store_value, accdesc);
if rt_unknown then
data = ARBITRARY : bits(128);
end;
if BigEndian(accdesc.acctype) then
X{64}(t) = data[127:64];
X{64}(t2) = data[63:0];
else
X{64}(t) = data[63:0];
X{64}(t2) = data[127:64];
end;
2026-03-12 12:23:09
2025-09_rel_asl1