TBL
Table vector lookup
This instruction reads each value from the vector elements in the index source SIMD&FP register,
uses each result as an index to perform a lookup in a table of bytes that
is described by one to four source table SIMD&FP registers,
places the lookup result in a vector, and writes
the vector to the destination SIMD&FP register.
If an index is out of range for the table, the result for that lookup is 0.
If more than one source register is used to describe the table,
the first source register describes the lowest bytes of the table.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>
0
1
TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>
1
0
TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>
1
1
TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV 8;
let regs : integer{} = UInt(len) + 1;
let is_tbl : boolean = (op == '0');
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Ta>
Is an arrangement specifier,
<Vn>
For the "Single register table" variant: is the name of the SIMD&FP table register, encoded in the "Rn" field.
<Vn>
For the "Four register table", "Three register table", and "Two register table" variants: is the name of the first SIMD&FP table register, encoded in the "Rn" field.
<Vm>
Is the name of the SIMD&FP index register, encoded in the "Rm" field.
<Vn+1>
Is the name of the second SIMD&FP table register, encoded as "Rn" plus 1 modulo 32.
<Vn+2>
Is the name of the third SIMD&FP table register, encoded as "Rn" plus 2 modulo 32.
<Vn+3>
Is the name of the fourth SIMD&FP table register, encoded as "Rn" plus 3 modulo 32.
AArch64_CheckFPAdvSIMDEnabled();
let indices : bits(datasize) = V{}(m);
var table : bits(128*regs) = Zeros{};
var result : bits(datasize);
var index : integer;
// Create table from registers
for i = 0 to regs - 1 do
table[i*:128] = V{128}((n+i) MOD 32);
end;
result = if is_tbl then Zeros{datasize} else V{datasize}(d);
for i = 0 to elements - 1 do
index = UInt(indices[i*:8]);
if index < 16 * regs then
result[i*:8] = table[index*:8];
end;
end;
V{datasize}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1