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<instructionsection id="TBNZ" title="TBNZ -- A64" type="instruction">
  <docvars>
    <docvar key="branch-offset" value="br14"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="TBNZ"/>
  </docvars>
  <heading>TBNZ</heading>
  <desc>
    <brief>
      <para>Test bit and branch if nonzero</para>
    </brief>
    <authored>
      <para>This instruction compares the value of a bit in a
general-purpose register with zero, and conditionally branches to
a label at a PC-relative offset if the comparison is not equal.
This instruction provides a hint that this is not a subroutine call or return.
This instruction does not affect condition flags.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="14-bit signed PC-relative branch offset" oneof="1" id="iclass_14_bit_signed_pc_relative_branch_offset" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="branch-offset" value="br14"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="TBNZ"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A64.control.testbranch.TBNZ_only_testbranch" tworows="1">
        <box hibit="31" width="1" name="b5" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="30" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="24" name="op" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="23" width="5" name="b40" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="18" width="14" name="imm14" usename="1">
          <c colspan="14"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="TBNZ_only_testbranch" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="branch-offset" value="br14"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="TBNZ"/>
        </docvars>
        <asmtemplate><text>TBNZ  </text><a hover="Is a width specifier, " link="R_option">&lt;R&gt;</a><a hover="Is the number [0-30] of the general-purpose register to be tested or the name ZR (31), encoded in the &quot;Rt&quot; field." link="Rt_option">&lt;t&gt;</a><text>, #</text><a hover="Is the bit number to be tested, in the range 0 to 63, encoded in &quot;b5:b40&quot;." link="b40_b5">&lt;imm&gt;</a><text>, </text><a hover="Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-32KB, is encoded as &quot;imm14&quot; times 4." link="imm14_offset">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.control.testbranch.TBNZ_only_testbranch" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer = UInt(Rt);

let datasize : integer{} = 32 &lt;&lt; UInt(b5);
let bit_pos : integer = UInt(b5::b40);
let offset : bits(64) = SignExtend{}(imm14::'00');</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="R_option">&lt;R&gt;</symbol>
      <definition encodedin="b5">
        <intro>Is a width specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">b5</entry>
                <entry class="symbol">&lt;R&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">W</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">X</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
        <after>In assembler source code an 'X' specifier is always permitted, but a 'W' specifier is only permitted when the bit number is less than 32.</after>
      </definition>
    </explanation>
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="Rt_option">&lt;t&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the number [0-30] of the general-purpose register to be tested or the name ZR (31), encoded in the "Rt" field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="b40_b5">&lt;imm&gt;</symbol>
      <account encodedin="(b40 :: b5)">
        <intro>
          <para>Is the bit number to be tested, in the range 0 to 63, encoded in "b5:b40".</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="TBNZ_only_testbranch" symboldefcount="1">
      <symbol link="imm14_offset">&lt;label&gt;</symbol>
      <account encodedin="imm14">
        <intro>
          <para>Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-32KB, is encoded as "imm14" times 4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.control.testbranch.TBNZ_only_testbranch" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">let operand : bits(datasize) = X{}(t);
let branch_conditional : boolean = TRUE;
if operand[bit_pos] != '0' then
    BranchTo{64}(PC64() + offset, BranchType_DIR, branch_conditional);
else
    BranchNotTaken(BranchType_DIR, branch_conditional);
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-12 12:23:09</timestamp>
  <commit_id>2025-09_rel_asl1</commit_id>
</instructionsection>
