UQXTN, UQXTN2
Unsigned saturating extract narrow
This instruction reads each vector element
from the source SIMD&FP register,
saturates each value to half the original width,
places the result into a vector,
and writes
the vector to the destination SIMD&FP
register.
All the values in this instruction are unsigned integer values.
If saturation occurs, the cumulative saturation bit
FPSR.QC is set.
The UQXTN instruction writes the vector
to the lower half of the
destination register and clears the upper half.
The UQXTN2 instruction writes the vector
to the upper half of the
destination register without affecting the other bits of the register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
1
1
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
0
UQXTN <Vb><d>, <Va><n>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size == '11' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = esize;
let part : integer = 0;
let elements : integer = 1;
let unsigned : boolean = TRUE;
0
1
0
1
1
1
0
1
0
0
0
0
1
0
1
0
0
1
0
UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size == '11' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = 64;
let part : integer = UInt(Q);
let elements : integer = datasize DIV esize;
let unsigned : boolean = TRUE;
<Vb>
Is the destination width specifier,
size
<Vb>
00
B
01
H
10
S
11
RESERVED
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<Va>
Is the source width specifier,
size
<Va>
00
H
01
S
10
D
11
RESERVED
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Tb>
Is an arrangement specifier,
size
Q
<Tb>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
x
RESERVED
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Ta>
Is an arrangement specifier,
size
<Ta>
00
8H
01
4S
10
2D
11
RESERVED
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(2*datasize) = V{}(n);
var result : bits(datasize);
var element : bits(2*esize);
var sat : boolean;
for e = 0 to elements-1 do
element = operand[e*:(2*esize)];
(result[e*:esize], sat) = SatQ{esize}(UInt(element), unsigned);
if sat then FPSR().QC = '1'; end;
end;
Vpart{datasize}(d, part) = result;
2026-03-12 12:23:09
2025-09_rel_asl1