USHLL, USHLL2 Unsigned shift left long (immediate) This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. The USHLL instruction extracts vector elements from the lower half of the source register. The USHLL2 instruction extracts vector elements from the upper half of the source register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. This instruction is used by the alias UXTL, UXTL2 immb == '000' && BitCount(immh) == 1 See below for details of when the alias is preferred. 0 1 0 1 1 1 1 0 != 0000 1 0 1 0 0 1 USHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift> if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; if immh[3] == '1' then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let esize : integer{} = 8 << HighestSetBitNZ(immh[2:0]); let datasize : integer{} = 64; let part : integer = UInt(Q); let elements : integer = datasize DIV esize; let shift : integer = UInt(immh::immb) - esize; let unsigned : boolean = TRUE; 2 Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is Q 2 0 [absent] 1 [present] <Vd> Is the name of the SIMD&FP destination register, encoded in the "Rd" field. <Ta> Is an arrangement specifier, immh <Ta> 0001 8H 001x 4S 01xx 2D 1xxx RESERVED <Vn> Is the name of the SIMD&FP source register, encoded in the "Rn" field. <Tb> Is an arrangement specifier, immh Q <Tb> 0001 0 8B 0001 1 16B 001x 0 4H 001x 1 8H 01xx 0 2S 01xx 1 4S 1xxx x RESERVED <shift> Is the left shift amount, in the range 0 to the source element width in bits minus 1, immh <shift> 0001 UInt(immh :: immb) - 8 001x UInt(immh :: immb) - 16 01xx UInt(immh :: immb) - 32 1xxx RESERVED Alias Conditions AArch64_CheckFPAdvSIMDEnabled(); let operand : bits(datasize) = Vpart{}(n, part); var result : bits(datasize*2); for e = 0 to elements-1 do let opelt : bits(esize) = operand[e*:esize]; let element : integer = if unsigned then UInt(opelt) else SInt(opelt); result[e*:(2*esize)] = (element << shift)[2*esize-1:0]; end; V{datasize*2}(d) = result; 2026-03-12 12:23:09 2025-09_rel_asl1